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Senior Applications Engineer - 72544



Senior Applications Engineer, SNF

The Stanford Nanofabrication Facility (SNF) serves researchers from other academic institutions and companies as well as Stanford.  We are a service organization providing research tools and know-how to over 400 researchers annually.  More about our operation can be found on our website ( 

We seek an experienced applications engineer who will join the senior staff in managing research operations.  The ideal candidate will have experience in electronics fabrication and deep knowledge of the equipment: a jack-or-jill-of-all-trades who is equally comfortable working side-by-side with researchers as well as troubleshooting equipment and facilities problems. 

The core responsibility of this position is oversight of Direct Patterning and Machining operations, which includes optical and electron-beam lithography, laser-cutting, milling, 3D printing, and supporting or related tools.  Specific experience in this capabilities is less important than keen interest in learning and teaching new technologies, as well as a deep understanding and demonstrated ability to apply engineering fundamentals.  Responsibilities include participation in the Incident Response Team supporting lab safety and providing local expertise in emergency events. As training is a core function of the SNF, keen interest in teaching as well as excellent written and oral communication skills, are required.


Job Title: Semiconductor Process Integration Modeling

Job Description: Applied Materials is looking for a Semiconductor Process Integration Engineer to help create the next generation semiconductor material processes and reactors via semiconductor process integration modeling. The process integration modeling expert will model the integration flow of the many process steps in a semiconductor fabrication process.  As the member of a larger Computer Aided Engineering (CAE) team you will play a key role in the development of Applied Materials chambers and processes.

Statement of Responsibilities and Duties:

  • Develop and maintain process integration flows to build different devices/structures (finfet, GAA, DRAM, SRAM, VNAND, BEOL interconnect, etc.) at different technology nodes
  • Apply process integration flows to study impact of deviations in flow to final device/structure build.
  • design for manufacturing such as unit process window analysis, across wafer variation studies, verify mask set layouts, impact of mask edge placement error, understand failure modes to improve yield such as defects and narrow process windows,
  • new integration development such as scaling studies, process/material substitutions, and assessing new process tool’s impact on integration
  • new novel device integration design such as plausibility / process feasibility (can it be made?) and verify all steps included to insure first silicon device build success
  • execute further analysis such as stress, RC extraction, and device modeling (i.e., electrical performance)
  • integration optimization such as tightening transistor performance variability or allow loosening of a tight process specification
  • Maintain awareness of technical literature, publish research results in peer-reviewed scientific or technical journals and present results at external conferences, seminars and/or technical meetings.
  • Perform other duties as assigned.


  • PhD in physics, electrical engineering, chemistry, or related field, or the equivalent combination of education and related experience.
  • Knowledge of semiconductor processes such as etch (ex: plasma, wet), deposition (ex: atomic layer deposition, chemical vapor deposition, physical vapor deposition), epitaxy, electroplating, thermal, doping, and other surface modification process (ex: nitridation, oxidation).
  • Knowledge of process steps required to build different semiconductor devices and structures.
  • Experience with tools such as Coventor’s SEMulator3D and synopsys’s spx: process explorer.
  • Understanding of process design kits (PDKs).
  • Interacts effectively with a broad range of colleagues such as hardware engineers, process engineers, program managers, and computational scientists.