From booth at snf.stanford.edu  Wed Aug  1 11:27:21 2001
From: booth at snf.stanford.edu (Len Booth)
Date: Wed, 01 Aug 2001 11:27:21 -0700
Subject: AG4108 quartzware changed to silicide
Message-ID: <3B684A09.961F2736@snf.stanford.edu>

The quartz chamber & the wafer tray have been
changed over.  The system is ready for silicidations.
Note:  because the quartz chamber was becomming dirty,
I installed the spare clean chamber - be sure to 
run a test wafer & verify the temperature of
your process/wafers, as the pyrometers may respond 
differently with the clean quartzware.
			Len


From balaji at sunray.snffab.stanford.edu  Tue Aug  7 10:37:38 2001
From: balaji at sunray.snffab.stanford.edu (Balaji Venkateshwaran)
Date: Tue, 7 Aug 2001 10:37:38 -0700 (PDT)
Subject: quartz tray change
Message-ID: <200108071737.KAA12430@sunray.snffab.stanford.edu>

I have requested for the diffusion tray to be installed in AG4108 on Wednesday.
Please let me know if anyone has a conflict with this.

Balaji



From booth at snf.stanford.edu  Fri Aug 10 15:10:17 2001
From: booth at snf.stanford.edu (Len Booth)
Date: Fri, 10 Aug 2001 15:10:17 -0700
Subject: AG4108 quartzware change
Message-ID: <3B745BC9.CFCD3CC4@snf.stanford.edu>

Users -
	The wafer tray has been cleaned & changed,
& the cassettes have been changed.
			Len


From balaji at sunray.snffab.stanford.edu  Fri Aug 10 16:26:19 2001
From: balaji at sunray.snffab.stanford.edu (Balaji Venkateshwaran)
Date: Fri, 10 Aug 2001 16:26:19 -0700 (PDT)
Subject: AG4108 usage
Message-ID: <200108102326.QAA14215@sunray.snffab.stanford.edu>

All,

I have signed up for AG4108 Monday AM and all day tuesday. If you are in rush to 
use it on Tuesday, please talk to me and we'll work something out.

Thanks,
Balaji
(408) 887-2056




From ehkim at stanford.edu  Tue Aug 14 10:17:19 2001
From: ehkim at stanford.edu (Eun-Ha Kim)
Date: Tue, 14 Aug 2001 10:17:19 -0700
Subject: AG4108 tray change
Message-ID: <001401c124e4$f96fed50$316340ab@EUN>

Hi 
I'd like to have the silicide tray installed tomorrow afternoon. 
If anyone has a conflict, please email me. Thanks.
______________________________

Yours truly,
Eun-Ha Kim      
 
CISX Building,  Rm 300
Stanford University
Stanford, CA 94305
Phone : (650) 725-0419
Email  : ehkim at stanford.edu
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From cmfaulkn at students.uiuc.edu  Tue Aug 14 11:01:30 2001
From: cmfaulkn at students.uiuc.edu (carl mccarty faulkner)
Date: Tue, 14 Aug 2001 13:01:30 -0500 (CDT)
Subject: AG4108 tray change
In-Reply-To: <001401c124e4$f96fed50$316340ab@EUN>
Message-ID: <Pine.GSO.4.31.0108141256370.11377-100000@ux10.cso.uiuc.edu>

I have scheduled time right before you Wednesday and may need it later
Wednesday night.  Can you postpone to Thursday?

Carl Faulkner


On Tue, 14 Aug 2001, Eun-Ha Kim wrote:

> Hi
> I'd like to have the silicide tray installed tomorrow afternoon.
> If anyone has a conflict, please email me. Thanks.
> ______________________________
>
> Yours truly,
> Eun-Ha Kim
>
> CISX Building,  Rm 300
> Stanford University
> Stanford, CA 94305
> Phone : (650) 725-0419
> Email  : ehkim at stanford.edu
>



From ehkim at stanford.edu  Tue Aug 14 15:04:22 2001
From: ehkim at stanford.edu (Eun-Ha Kim)
Date: Tue, 14 Aug 2001 15:04:22 -0700
Subject: AG4108 tray change (Thursday)
Message-ID: <008501c1250d$1324dcb0$316340ab@EUN>

Hi all,
So far I've heard from Carl who wants to have oxidation tray till Wednesday
night.
I'm deleting my reservation tomorrow, rescheduling it to Thursday morning,
and hoping to have silicide tray installed for Thursday.
If you still have a conflict, please let me know.
 ______________________________
 
Yours truly,
Eun-Ha Kim
 
CISX Building,  Rm 300
Stanford University
Stanford, CA 94305
Phone : (650) 725-0419
Email  : ehkim at stanford.edu
 
> ----- Original Message -----
> From: "carl mccarty faulkner" <cmfaulkn at students.uiuc.edu>
> To: "Eun-Ha Kim" <ehkim at Stanford.EDU>
> Cc: <ag4108 at snf.stanford.edu>
> Sent: Tuesday, August 14, 2001 11:01 AM
> Subject: Re: AG4108 tray change
> 
> 
> > I have scheduled time right before you Wednesday and may need it later
> > Wednesday night.  Can you postpone to Thursday?
> >
> > Carl Faulkner
> 
> 



From mcvittie at cis.Stanford.EDU  Thu Aug 16 22:02:33 2001
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Thu, 16 Aug 2001 22:02:33 -0700 (PDT)
Subject: Ge into RTA (AG4108)
In-Reply-To: <001801c12693$b909a6b0$316340ab@EUN>
Message-ID: <Pine.SOL.4.05.10108162151160.14678-100000@cis>

AG4108 Users,

Eun-Ha Kim, who is one of Plummer's students, wants to do Ge anneals in
the 4108. The Ge will be on Si wafers. Since GeO2 is pretty volatile, I am
a little concerned about Ge contamination.  To avoid that problem, she has
offered to cover her wafer with LTO.

How concerned are you with Ge contamination and if you are concerned, do
you have any objections if a LTO cover is used? The only possible Ge
contamination problem that I am aware of is that GeSi does not have as
good of an oxide interface as pure Si has.

	Thanks,		Jim 	
--------------------------------------------------------------
James P. McVittie	                Senior Research Scientist
Allen Center for Integrated Systems     jmcvittie at stanford.edu
Stanford University             	Tel: (650) 725-3640	
Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
Stanford, CA 94305-4075	

On Thu, 16 Aug 2001, Eun-Ha Kim wrote:

> Hi Jim,
> I am hoping to get RTA done with my samples. They are implanted 1000A-germanium thin films on silicon wafers in order to study common dopant's activation behavior in germanium. If I have to worry about oxidation of Ge, I can deposit LTO on top of Ge or do something to prevent it. Please let me know what you think of. Thanks. 
> ______________________________
> 
> Yours truly,
> Eun-Ha Kim      
>  
> CISX Building,  Rm 300
> Stanford University
> Stanford, CA 94305
> Phone : (650) 725-0419
> Email  : ehkim at stanford.edu
> 



From booth at snf.stanford.edu  Fri Aug 17 10:53:48 2001
From: booth at snf.stanford.edu (Len Booth)
Date: Fri, 17 Aug 2001 10:53:48 -0700
Subject: AG4108 quartzware change to silicide
Message-ID: <3B7D5A2C.FF522D51@snf.stanford.edu>

	The AG4108 quartzware has been changed from
oxidation to silicide, and the cassettes have been
swapped.		Len


From dhelqaq at hotmail.com  Fri Aug 17 13:35:20 2001
From: dhelqaq at hotmail.com (Deirdre Heyde Elqaq)
Date: Fri, 17 Aug 2001 13:35:20 -0700
Subject: Ge into RTA (AG4108)
Message-ID: <F29iJBNDymPUVhV3Ca30000ac9a@hotmail.com>

All/Dr. McVittie,

As far as the Intel group at CIS is concerned, we do not see Ge as an issue 
for us as long as the sample is capped with oxide as was mentioned in the 
email below.
Kind regards,
Deirdre Heyde Elqaq

>
> >From: Jim McVittie <mcvittie at cis.Stanford.EDU>
> >To: ag4108 at snf.stanford.edu
> >CC: Eun-Ha Kim <ehkim at Stanford.EDU>
> >Subject: Re: Ge into RTA (AG4108)
> >Date: Thu, 16 Aug 2001 22:02:33 -0700 (PDT)
> >
> >AG4108 Users,
> >
> >Eun-Ha Kim, who is one of Plummer's students, wants to do Ge anneals in
> >the 4108. The Ge will be on Si wafers. Since GeO2 is pretty volatile, I 
>am
> >a little concerned about Ge contamination.  To avoid that problem, she 
>has
> >offered to cover her wafer with LTO.
> >
> >How concerned are you with Ge contamination and if you are concerned, do
> >you have any objections if a LTO cover is used? The only possible Ge
> >contamination problem that I am aware of is that GeSi does not have as
> >good of an oxide interface as pure Si has.
> >
> >	Thanks,		Jim
> >--------------------------------------------------------------
> >James P. McVittie	                Senior Research Scientist
> >Allen Center for Integrated Systems     jmcvittie at stanford.edu
> >Stanford University             	Tel: (650) 725-3640
> >Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
> >Stanford, CA 94305-4075
> >
> >On Thu, 16 Aug 2001, Eun-Ha Kim wrote:
> >
> > > Hi Jim,
> > > I am hoping to get RTA done with my samples. They are implanted
> >1000A-germanium thin films on silicon wafers in order to study common
> >dopant's activation behavior in germanium. If I have to worry about
> >oxidation of Ge, I can deposit LTO on top of Ge or do something to 
>prevent
> >it. Please let me know what you think of. Thanks.
> > > ______________________________
> > >
> > > Yours truly,
> > > Eun-Ha Kim
> > >
> > > CISX Building,  Rm 300
> > > Stanford University
> > > Stanford, CA 94305
> > > Phone : (650) 725-0419
> > > Email  : ehkim at stanford.edu
> > >
> >
>
>
>_________________________________________________________________
>Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
>
>


_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp



From mcvittie at cis.Stanford.EDU  Tue Aug 21 10:45:56 2001
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Tue, 21 Aug 2001 10:45:56 -0700 (PDT)
Subject: Replies on Deep Ge in Si 
Message-ID: <Pine.SOL.4.05.10108211038461.1992-100000@cis>

AG4108 Users,

Ge does not appear to be a problem in Si. Concerning Ge causing a deep
level in Si, I sent out the following question to three researchers
working in the SiGe area. Included below are thier replies which all say 
Ge should not be a concern.

	Jim McVittie 

To: Dan Connelly, Tsu-Jae King (Berkeley) and Judy Hoyt (MIT)
> One of the students just pointed out to me, Ge has a donor level of
> 0.5 eV in silicon according Sze's book. The Bell labs Quick Refernce
> Manual says that this 0.5 eV level comes from capacitance studies done
> by Fahrner and Goetzberger in 1972.
>
> My question to you is, do I have to worry about Ge being a lifetime
> killer in Si devices if I allow SiGe processing in the same equipment
> as my Si devices? So far, we have not been that fussy about keeping Ge
> out of the Si equipment except for a few oxidation tubes.  We have not
> seen any problems but we have not looked very carefully either.  By
> the way, I have heard that AMD restricts Ge use from more equipment
> than they do for Ni.
>
>                 Thanks, Jim  

---------------
Date: Mon, 20 Aug 2001 17:10:10 -0700
From: Daniel Connelly <djconnel at ieee.org>   

At Motorola, Ge contamination of Si wasn't considered a problem. I've not
seen anything which suggests it contributes to a degration of lifetime,
other than band structure effects at alloy concentrations.  So I know of
no cause for concern.

Dan     

-------------------
Date: Mon, 20 Aug 2001 18:16:53 -0700
From: Tsu Jae King <tking at eecs.berkeley.edu>

If Ge exists at the Si/SiO2 interface, it will serve as a carrier trap. If
Ge exists in the Si bulk, it simply forms an alloy and does not act as a
trap which kills minority carrier lifetime.  IBM (and now other companies)
use SiGe-base NPN transistors for their high-performance communications
products. The fact that high current gain is achieved with this
heterojunction BJT technology proves that Ge does not kill the minority
carrier lifetime in Si. The bandgap of SiGe decreases with increasing Ge
content, so pn junction leakage will be higher if SiGe is used on either
side of the junction.

--------------------
Date: Mon, 20 Aug 2001 21:59:56 -0400
From: Judy L. Hoyt <jlhoyt at mtl.mit.edu>

I remember seeing that in Sze and wondering about it, since many
people have produced very high lifetime SiGe samples.  In general,
I am not concerned about Ge from SiGe epi layers.  It is not known
to be a lifetime killer and is a very slow diffuser in Si and SiO2, unlike
most
metals.

More of a concern is how the SiGe was grown (in what equipment/reactor),
because the cleanliness of the growth system and gases used
is likely to be more of an issue than the Ge itself.

I'm not sure why some companies are so restrictive about Ge while
others have no issue.  My guess is that it is largely due to the level of
experience - at the start, people seem to be very conservative, and  
with time confidence builds.

If there are specific concerns, feel free to ask, but I would be much
more restrictive with Ni than with Ge, for sure.     





From intelbalaji at yahoo.com  Tue Aug 21 11:07:10 2001
From: intelbalaji at yahoo.com (Balaji Venkateshwaran)
Date: Tue, 21 Aug 2001 11:07:10 -0700 (PDT)
Subject: tray change to oxidation
Message-ID: <20010821180710.9618.qmail@web12806.mail.yahoo.com>

I have requested for a tray change on AG4108 to
oxidation. Len may change it tomorrow as there are no
sign-ups to use it in silicide mode. Please let me
know if there is a conflict.

Balaji


__________________________________________________
Do You Yahoo!?
Make international calls for as low as $.04/minute with Yahoo! Messenger
http://phonecard.yahoo.com/


From booth at snf.stanford.edu  Wed Aug 22 11:21:38 2001
From: booth at snf.stanford.edu (Len Booth)
Date: Wed, 22 Aug 2001 11:21:38 -0700
Subject: Quartzware change to oxidation
Message-ID: <3B83F832.519DA8E0@snf.stanford.edu>

I have changed the quartzware from silicide to
oxidation, also the cassettes & the sign.
			Len


From ehkim at stanford.edu  Mon Aug 27 11:16:15 2001
From: ehkim at stanford.edu (Eun-Ha Kim)
Date: Mon, 27 Aug 2001 11:16:15 -0700
Subject: AG4108 : tray change to silicide
Message-ID: <004301c12f24$5c5cd380$316340ab@EUN>

Hi 
I'd like to have the silicide tray installed this Wednesday, 8/29. 
If anyone has a conflict, please email me. Thanks.
______________________________

Yours truly,
Eun-Ha Kim      
 
CISX Building,  Rm 300
Stanford University
Stanford, CA 94305
Phone : (650) 725-0419
Email  : ehkim at stanford.edu
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From mtang at snf.stanford.edu  Wed Aug 29 09:48:46 2001
From: mtang at snf.stanford.edu (Mary Tang)
Date: Wed, 29 Aug 2001 09:48:46 -0700
Subject: Help?
Message-ID: <3B8D1CEE.E67C6E8@snf.stanford.edu>

Hello "ag4108" users --

Would any of you be willing to perform an act in the name of "community
service" and train me and one other wannabe-user on the ag4108?  (Then I
can become the ag4108 queen and will handle future training...)

Mary


--
Mary X. Tang, Ph.D.
National Nanofabrication Users' Network
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at snf.stanford.edu