Problem amtetcher SNF 2012-12-12 15:27:11: Low silicon etch rate on recipe 4 ...

shott at snf.stanford.edu shott at snf.stanford.edu
Fri Jan 11 13:03:36 PST 2013


We were trying to etch some ASML global alignment marks on a set of wafers.  We used recipe 4 for a time of 6 minutes and expected and etch depth of about 0.125 to 0.150 um.  A Zygo measurement after resist strip of a single wafer showed a step heigh of only about 0.038 um.
The wafers had a 2 mm edge bead of exposed silicon and 4 of the global aligment marks spaced about 6 mm in from the edge of the wafer.  As a result, the edge bead dominated the exposed area of silicon.
Each run that 3 pallets (12 wafers) of these wafers with the remaining 3 pallets containing dummies.
If you are etching global alignment marks for the ASML, please proceed with caution.
Resist coating was 1 um of 3612 resist.
John



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