From mahnaz at stanford.edu  Fri Feb  1 17:10:04 2008
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Fri, 01 Feb 2008 17:10:04 -0800
Subject: [Fwd: epi backsides]
Message-ID: <47A3C2EC.5010407@stanford.edu>


Hello all,

Here are the pictures of the EPI wafers ( back side)  that lost vacuum 
on the asml.
We are looking in to the issue from different angle.
Binder is going to send the pictures to Europe and seek their advise.
One thought was,  that may be one of the pin in EPI  is not performing 
well so Maurice went through the trouble to open the system and let me 
look in to it,   and things looks to be just fine,  Gary Yama confirmed 
it as well. Still Maurice will peruse the issue to see why we see this 
problem with thicker deposition.
Apparently few lab members already figure out how to approach  and 
resolve the issue for their process;
Renata  does some sort of CMP, Yuhykr deposit LTO first and that  has 
worked for him well. Gary Yama has an idea which we will discuss  next 
week.  We are all   trying to find the easiest way  which will work for 
every one and does not require many extra steps. So till next week,  be 
patient and work with us.
Thanks to maurice for taking the  pictures.


mahnaz
-------- Original Message --------
Subject: epi backsides
Date: Fri, 01 Feb 2008 13:22:39 -0800
From: maurice <maurice at snf.stanford.edu>
To: Mahnaz Mansourpour <mahnaz at snf.stanford.edu>



The message is ready to be sent with the following file or link 
attachments:
P1010100
P1010099




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From nandasiri.samarakone at asml.com  Fri Feb  1 18:19:05 2008
From: nandasiri.samarakone at asml.com (Nandasiri Samarakone)
Date: Fri, 1 Feb 2008 21:19:05 -0500
Subject: [Fwd: epi backsides]
In-Reply-To: <47A3C2EC.5010407@stanford.edu>
Message-ID: <25C387066C812B47BBB8B617C867C377BFDF81@USWILX85.sn-us.asml.com>

Hi Binder
 
Please touch base with me Monday so we can discuss.
 
What I gather from Mahnaz mail is that thick epi wafers wont hold on the
ASML
 
Usually thats due to wafer warpage 
 
The picture suggests an area of epi that has a different grain structure
and hence reflectivity.
 
I expect epi dep to be single sided so it points to some kind of
different grain nucleation mechanism in that area which presumably is
temperature related and hence stress will cause wafer bow.
 
I am not an expert on epi, however, my involvements in silicon on
sapphire epi dep and poly deposition would suggest that dropping the
deposition temperature and aiming for a slower growth rate may help.
 
Anyway lets discuss, before we involve Europe. 
 
Thanks
 
Nanda

________________________________

From: Mahnaz Mansourpour [mailto:mahnaz at stanford.edu] 
Sent: Friday, February 01, 2008 5:10 PM
To: asml at snf.stanford.edu; Paul Rissman; Mary Tang; Nandasiri Samarakone
Subject: [Fwd: epi backsides]



Hello all,

Here are the pictures of the EPI wafers ( back side)  that lost vacuum
on the asml.
We are looking in to the issue from different angle.
Binder is going to send the pictures to Europe and seek their advise.
One thought was,  that may be one of the pin in EPI  is not performing
well so Maurice went through the trouble to open the system and let me
look in to it,   and things looks to be just fine,  Gary Yama confirmed
it as well. Still Maurice will peruse the issue to see why we see this
problem with thicker deposition.
Apparently few lab members already figure out how to approach  and
resolve the issue for their process; 
Renata  does some sort of CMP, Yuhykr deposit LTO first and that  has
worked for him well. Gary Yama has an idea which we will discuss  next
week.  We are all   trying to find the easiest way  which will work for
every one and does not require many extra steps. So till next week,  be
patient and work with us. 
Thanks to maurice for taking the  pictures.


mahnaz
-------- Original Message -------- 
Subject: 	epi backsides	
Date: 	Fri, 01 Feb 2008 13:22:39 -0800	
From: 	maurice <maurice at snf.stanford.edu>
<mailto:maurice at snf.stanford.edu> 	
To: 	Mahnaz Mansourpour <mahnaz at snf.stanford.edu>
<mailto:mahnaz at snf.stanford.edu> 	


The message is ready to be sent with the following file or link 
attachments:
P1010100
P1010099





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From rmelamud at stanford.edu  Mon Feb  4 18:42:46 2008
From: rmelamud at stanford.edu (rmelamud at stanford.edu)
Date: Mon, 04 Feb 2008 18:42:46 -0800
Subject: asml: Tues 8am res removed
Message-ID: <20080204184246.6rs4blbl5w4s0g88@webmail.stanford.edu>




From mahnaz at stanford.edu  Fri Feb 15 15:33:46 2008
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Fri, 15 Feb 2008 15:33:46 -0800
Subject: Hoe to test for flatness
Message-ID: <47B6215A.8020402@stanford.edu>


Hello all,

Here is a quick reference of how to do this test, but the truth is that 
the granite table  is very flat.

mahnaz
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From mahnaz at stanford.edu  Wed Feb 27 14:37:57 2008
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Wed, 27 Feb 2008 14:37:57 -0800
Subject: up date
Message-ID: <47C5E645.1000307@stanford.edu>


Hello all,

I like to let every one  know that 3D align installation and 
qualification is on the way.
we    ASML and SNF people are trying to get all the facts/ tests, date 
scheduled in a way that minimize  equipment down time as much as 
possible. My understanding is that the system needs to be switched to 6" 
till all the quals and tests ran.  As of right now,  we think that the 
system will be down for two weeks  and we are aiming for  mid April. I 
thought to give you heads up regarding this matter and still there are 
good possibility that dates can get changed around a bit.
Please  let me know if  there are any other issues that we should 
consider or any one out there has a serious dead line ( I need to hear 
from you).

mahnaz