From mahnaz at stanford.edu  Mon May 11 13:22:08 2009
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Mon, 11 May 2009 13:22:08 -0700
Subject: asml demo
Message-ID: <4A0888F0.7070803@stanford.edu>

Hello all,

I like to let you know that the stepper will be down on May 26th and 27th.
Asml needs  to do a demo so on Tuesday 26th we will have access to asml 
till 10:30 am and then the system will switch to 3" and will stay in 3" 
till 2:30 pm on 27th. In short the system will be unavailable from mid 
day on 26th till 2:30 on 27th.
Please plan accordingly.

mahnaz


From gthareja at stanford.edu  Wed May 13 15:22:12 2009
From: gthareja at stanford.edu (Gaurav Thareja)
Date: Wed, 13 May 2009 15:22:12 -0700 (PDT)
Subject: Alignment marks etched in LTO ?
Message-ID: <1777353807.3584351242253332526.JavaMail.root@zm06.stanford.edu>

Dear ASML users.

Does anybody have any experience in etching and aligning ASML alignment marks in LTO or Thermal Oxide (instead of etching in the substrate) ?

please let me know

warm regards
~gaurav

-- 
Gaurav Thareja
Ph.D candidate, Nishi group
Electrical Engineering
Stanford University
420 Via Palou Mall, CISX 128
Stanford, CA 94305
Tel: 650-704-1029
Email: gthareja at stanford.edu


From jimkruger at yahoo.com  Wed May 13 15:40:58 2009
From: jimkruger at yahoo.com (jim kruger)
Date: Wed, 13 May 2009 15:40:58 -0700 (PDT)
Subject: Alignment marks etched in LTO ?
Message-ID: <475253.74352.qm@web38902.mail.mud.yahoo.com>


I have etched (wet) into 1000A thermal Oxide on Si.  Seems to work fine.  I have not tried to overlay more than 2 levels with this.

jim

--- On Wed, 5/13/09, Gaurav Thareja <gthareja at stanford.edu> wrote:

> From: Gaurav Thareja <gthareja at stanford.edu>
> Subject: Alignment marks etched in LTO ?
> To: asml at snf.stanford.edu
> Date: Wednesday, May 13, 2009, 3:22 PM
> Dear ASML users.
> 
> Does anybody have any experience in etching and aligning
> ASML alignment marks in LTO or Thermal Oxide (instead of
> etching in the substrate) ?
> 
> please let me know
> 
> warm regards
> ~gaurav
> 
> -- 
> Gaurav Thareja
> Ph.D candidate, Nishi group
> Electrical Engineering
> Stanford University
> 420 Via Palou Mall, CISX 128
> Stanford, CA 94305
> Tel: 650-704-1029
> Email: gthareja at stanford.edu
> 


      


From edmyers at stanford.edu  Thu May 14 12:25:17 2009
From: edmyers at stanford.edu (Ed Myers)
Date: Thu, 14 May 2009 12:25:17 -0700
Subject: Alignment marks etched in LTO ?
In-Reply-To: <475253.74352.qm@web38902.mail.mud.yahoo.com>
References: <475253.74352.qm@web38902.mail.mud.yahoo.com>
Message-ID: <6.2.5.6.2.20090514122042.027e0338@stanford.edu>

All,

Be careful.  We have seen alignment marks which are marginal and work 
for a number of layers but not for your whole process.  If Jim pulled 
his batch data and saw a strong signal, I would feel more 
comfortable.  The system has a large capture range, which is why some 
are lead to believe the marks are fine when in reality they are 
extremely marginal.

ASML engineers have a simulation program which they can use to 
determine the correct alignment mark depth for the various films.  I 
recommend we contact ASML to run the simulation and also verify the 
quality of the alignment mark before I would commit my wafers.

How many times have you heard "it aligned at the last layer."  Many 
times this came from marginal alignment marks.

Ed


At 03:40 PM 5/13/2009, jim kruger wrote:

>I have etched (wet) into 1000A thermal Oxide on Si.  Seems to work 
>fine.  I have not tried to overlay more than 2 levels with this.
>
>jim
>
>--- On Wed, 5/13/09, Gaurav Thareja <gthareja at stanford.edu> wrote:
>
> > From: Gaurav Thareja <gthareja at stanford.edu>
> > Subject: Alignment marks etched in LTO ?
> > To: asml at snf.stanford.edu
> > Date: Wednesday, May 13, 2009, 3:22 PM
> > Dear ASML users.
> >
> > Does anybody have any experience in etching and aligning
> > ASML alignment marks in LTO or Thermal Oxide (instead of
> > etching in the substrate) ?
> >
> > please let me know
> >
> > warm regards
> > ~gaurav
> >
> > --
> > Gaurav Thareja
> > Ph.D candidate, Nishi group
> > Electrical Engineering
> > Stanford University
> > 420 Via Palou Mall, CISX 128
> > Stanford, CA 94305
> > Tel: 650-704-1029
> > Email: gthareja at stanford.edu
> >
>
>
>




From mahnaz at stanford.edu  Thu May 14 13:03:13 2009
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Thu, 14 May 2009 13:03:13 -0700
Subject: Alignment marks etched in LTO ?
In-Reply-To: <6.2.5.6.2.20090514122042.027e0338@stanford.edu>
References: <475253.74352.qm@web38902.mail.mud.yahoo.com> <6.2.5.6.2.20090514122042.027e0338@stanford.edu>
Message-ID: <4A0C7901.2040302@stanford.edu>

The recommendation was made to Gaurav yesterday during training.

mahnaz

Ed Myers wrote:
> All,
>
> Be careful.  We have seen alignment marks which are marginal and work 
> for a number of layers but not for your whole process.  If Jim pulled 
> his batch data and saw a strong signal, I would feel more 
> comfortable.  The system has a large capture range, which is why some 
> are lead to believe the marks are fine when in reality they are 
> extremely marginal.
>
> ASML engineers have a simulation program which they can use to 
> determine the correct alignment mark depth for the various films.  I 
> recommend we contact ASML to run the simulation and also verify the 
> quality of the alignment mark before I would commit my wafers.
>
> How many times have you heard "it aligned at the last layer."  Many 
> times this came from marginal alignment marks.
>
> Ed
>
>
> At 03:40 PM 5/13/2009, jim kruger wrote:
>
>> I have etched (wet) into 1000A thermal Oxide on Si.  Seems to work 
>> fine.  I have not tried to overlay more than 2 levels with this.
>>
>> jim
>>
>> --- On Wed, 5/13/09, Gaurav Thareja <gthareja at stanford.edu> wrote:
>>
>> > From: Gaurav Thareja <gthareja at stanford.edu>
>> > Subject: Alignment marks etched in LTO ?
>> > To: asml at snf.stanford.edu
>> > Date: Wednesday, May 13, 2009, 3:22 PM
>> > Dear ASML users.
>> >
>> > Does anybody have any experience in etching and aligning
>> > ASML alignment marks in LTO or Thermal Oxide (instead of
>> > etching in the substrate) ?
>> >
>> > please let me know
>> >
>> > warm regards
>> > ~gaurav
>> >
>> > --
>> > Gaurav Thareja
>> > Ph.D candidate, Nishi group
>> > Electrical Engineering
>> > Stanford University
>> > 420 Via Palou Mall, CISX 128
>> > Stanford, CA 94305
>> > Tel: 650-704-1029
>> > Email: gthareja at stanford.edu
>> >
>>
>>
>>
>
>


From chen0622 at yahoo.com  Mon May 18 08:43:59 2009
From: chen0622 at yahoo.com (c.c.)
Date: Mon, 18 May 2009 08:43:59 -0700 (PDT)
Subject: ASML today reservation released 12:00 PM to 1:00 PM
Message-ID: <237134.88811.qm@web56805.mail.re3.yahoo.com>

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