Alignment marks etched in LTO ?
mahnaz at stanford.edu
Thu May 14 13:03:13 PDT 2009
The recommendation was made to Gaurav yesterday during training.
Ed Myers wrote:
> Be careful. We have seen alignment marks which are marginal and work
> for a number of layers but not for your whole process. If Jim pulled
> his batch data and saw a strong signal, I would feel more
> comfortable. The system has a large capture range, which is why some
> are lead to believe the marks are fine when in reality they are
> extremely marginal.
> ASML engineers have a simulation program which they can use to
> determine the correct alignment mark depth for the various films. I
> recommend we contact ASML to run the simulation and also verify the
> quality of the alignment mark before I would commit my wafers.
> How many times have you heard "it aligned at the last layer." Many
> times this came from marginal alignment marks.
> At 03:40 PM 5/13/2009, jim kruger wrote:
>> I have etched (wet) into 1000A thermal Oxide on Si. Seems to work
>> fine. I have not tried to overlay more than 2 levels with this.
>> --- On Wed, 5/13/09, Gaurav Thareja <gthareja at stanford.edu> wrote:
>> > From: Gaurav Thareja <gthareja at stanford.edu>
>> > Subject: Alignment marks etched in LTO ?
>> > To: asml at snf.stanford.edu
>> > Date: Wednesday, May 13, 2009, 3:22 PM
>> > Dear ASML users.
>> > Does anybody have any experience in etching and aligning
>> > ASML alignment marks in LTO or Thermal Oxide (instead of
>> > etching in the substrate) ?
>> > please let me know
>> > warm regards
>> > ~gaurav
>> > --
>> > Gaurav Thareja
>> > Ph.D candidate, Nishi group
>> > Electrical Engineering
>> > Stanford University
>> > 420 Via Palou Mall, CISX 128
>> > Stanford, CA 94305
>> > Tel: 650-704-1029
>> > Email: gthareja at stanford.edu
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