From mahnaz at stanford.edu Wed Apr 4 10:48:52 2012 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Wed, 04 Apr 2012 10:48:52 -0700 Subject: Purge hood Message-ID: <4F7C8984.4040804@stanford.edu> Hello all, I have made reservation for Monday 4/9 all morning. The purge hood in the system needs height adjustment. The purge hood will allow us to run thick resist 220-3, 220-7 in the system. Please use the system till staff actually shuts down the tool for the work, it might be a quick job or might take till 2:30 pm. I apologize for any inconvenient this may cause. mahnaz From mahnaz at stanford.edu Wed Apr 4 15:15:59 2012 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Wed, 04 Apr 2012 15:15:59 -0700 Subject: ASML Monthly pm Message-ID: <4F7CC81F.3070303@stanford.edu> Hello all, ASML monthly pm has been scheduled for April 17,18th. ASMl like to reserve the 4/19 ( tentatively) to trouble shoot the optic ( drop in lamp intensity). Please plan accordingly. Litho staff From cmcg at stanford.edu Thu Apr 12 13:55:55 2012 From: cmcg at stanford.edu (Chris McGuinness) Date: Thu, 12 Apr 2012 13:55:55 -0700 (PDT) Subject: asml free today 4:30-7pm (EOM) Message-ID: <1740163380.6870878.1334264155667.JavaMail.root@zm10.stanford.edu> From cmcg at stanford.edu Fri Apr 13 15:39:59 2012 From: cmcg at stanford.edu (Chris McGuinness) Date: Fri, 13 Apr 2012 15:39:59 -0700 (PDT) Subject: asml up and free 4-6pm Message-ID: <309930550.7750277.1334356799507.JavaMail.root@zm10.stanford.edu> happy processing From mahnaz at stanford.edu Fri Apr 13 16:04:50 2012 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 13 Apr 2012 16:04:50 -0700 Subject: Warp wafers, please read Message-ID: <4F88B112.4060106@stanford.edu> Hello all, I have added this to the procedure, so please read, and Wiki has been updated as well. Many times I get the answer that my wafer ran last time or i did not know so this will get your attention *Addition of every layer will add more stress to the wafer; it is your responsibility to check the wafer flatness at each step before using the ASML. Warp wafers has to be planned (Linda, Gary and Mahnaz) and ran during the day only then we will accept the responsibility of getting the tool stuck. Getting the tool stuck is time consuming and expensive so you need to do your part. Ifwafers get stuck in the system due to beingwarpor , dirt ( residue, scratches on the back of wafers) and stress around the edge of wafers, all the time that system is down due to wafer gotten stuck your account will be charged and you will be up for community service, No exception.* *If you have any question you are welcome to talk to John Bumgarner.* ** ** *Wafer Flatness test for ASML* This test is done on the Rock/Granite/table in the characterization room. Clean the Right side of the table with IPA and wipes. Put your wafer on the table/granite if the wafer SLIDE, the wafer is FLAT if not then is NOT flat. If the wafer is not flat you should wait and check with staff (Linda,Gary and I) before committing your wafers. Please do not take a chance by running nonstandard wafers that are not FLAT, damaged, stressedor something on the back of wafers and you are not able to take it off for any reason off hours, the system will shut down and I will take your name off the system and every one will hate you.For wafers of this nature we can discuss the issue and try to process it and during the day when both ASML and us are here (there is always hope). I have put two wafers on the Granite/ table which are labeled FLAT and NOT FLAT for you to see the difference. *We have Stresstest tool as well, we strongly suggest if you are doing multilayer or thick depositions check the wafer stress at each level starting with first layer to establish a baseline. * mahnaz ** ** -------------- next part -------------- An HTML attachment was scrubbed... URL: From mahnaz at stanford.edu Fri Apr 13 16:27:34 2012 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 13 Apr 2012 16:27:34 -0700 Subject: particle on the chuck Message-ID: <4F88B666.609@stanford.edu> Hi all, take every precaution to not contaminate the chuck. We started having issue again with swinging the table in/out. mahnaz From qran at stanford.edu Mon Apr 23 11:44:18 2012 From: qran at stanford.edu (Helen Qiushi Ran) Date: Mon, 23 Apr 2012 11:44:18 -0700 (PDT) Subject: asml time release from 2:30pm to 3:30pm (EOM) Message-ID: <1779032728.53227748.1335206658975.JavaMail.root@zm04.stanford.edu> Helen Qiushi Ran ========================================= Department of Electrical Engineering Stanford University, Stanford, CA 94305. Mobile: +1-650-796-1439 Email: qran at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From cfchiang at stanford.edu Wed Apr 25 20:49:46 2012 From: cfchiang at stanford.edu (Chia-Fang Chiang) Date: Wed, 25 Apr 2012 20:49:46 -0700 (PDT) Subject: ASML release tonight 10-11pm (eom) In-Reply-To: <1989590802.64418236.1335412176125.JavaMail.root@zm06.stanford.edu> Message-ID: <1750233560.64418473.1335412186251.JavaMail.root@zm06.stanford.edu> -------------- next part -------------- An HTML attachment was scrubbed... URL: From raneeyoo at stanford.edu Wed Apr 25 21:41:06 2012 From: raneeyoo at stanford.edu (Kyeongran Yoo) Date: Wed, 25 Apr 2012 21:41:06 -0700 (PDT) Subject: ASML release tonight 10-11pm (eom) In-Reply-To: <1750233560.64418473.1335412186251.JavaMail.root@zm06.stanford.edu> Message-ID: <983886831.64450390.1335415266136.JavaMail.root@zm06.stanford.edu> I will take it. thanks. ----- Original Message ----- From: "Chia-Fang Chiang" To: asml at snf.stanford.edu Sent: Wednesday, April 25, 2012 8:49:46 PM Subject: ASML release tonight 10-11pm (eom)