Warp wafers, please read

Mahnaz Mansourpour mahnaz at stanford.edu
Fri Apr 13 16:04:50 PDT 2012


Hello all,

I have added this to the procedure, so please read,  and  Wiki has been 
updated as well.

Many times  I get the answer that my wafer ran last time or i did  not 
know so
this will get your attention



*Addition of every layer will add more stress to the wafer; it is your 
responsibility to check the wafer flatness at each step before using the 
ASML. Warp wafers has to be planned (Linda, Gary and Mahnaz) and ran 
during the day only then we will accept the responsibility of getting 
the tool stuck. Getting the tool stuck is time consuming and expensive 
so you need to do your part. Ifwafers get stuck in the system due to 
beingwarpor , dirt ( residue, scratches on the back of wafers) and 
stress around the edge of wafers, all the time that system is down due 
to wafer gotten stuck your account will be charged and you will be up 
for community service, No exception.*

*If you have any question you are welcome to talk to John Bumgarner.*

**

**

*Wafer Flatness test for ASML*

This test is done on the Rock/Granite/table in the characterization room.

Clean the Right side of the table with IPA and wipes.

Put your wafer on the table/granite if the wafer SLIDE, the wafer is 
FLAT if not then is NOT flat. If the wafer is not flat you should wait 
and check with staff (Linda,Gary and I) before committing your wafers.

Please do not take a chance by running nonstandard wafers that are not 
FLAT, damaged, stressedor something on the back of wafers and you are 
not able to take it off for any reason off hours, the system will shut 
down and I will take your name off the system and every one will hate 
you.For wafers of this nature we can discuss the issue and try to 
process it and during the day when both ASML and us are here (there is 
always hope).

I have put two wafers on the Granite/ table which are labeled FLAT and 
NOT FLAT for you to see the difference.

*We have Stresstest  tool as well, we strongly suggest if you are doing 
multilayer or thick depositions check the wafer stress at each level 
starting with first layer to establish a baseline.
*


mahnaz
**

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