From mahnaz at stanford.edu  Wed Oct  3 07:54:33 2012
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Wed, 03 Oct 2012 07:54:33 -0700
Subject: thick resist use
In-Reply-To: <CAPwL1Nq2BkMcpWdHEW7VrAHUHH_soZUZvDMUN-37bEFaQNscjA@mail.gmail.com>
References: <CAPwL1Nq2BkMcpWdHEW7VrAHUHH_soZUZvDMUN-37bEFaQNscjA@mail.gmail.com>
Message-ID: <506C51A9.6090100@stanford.edu>

Hi Edgar,

For time being we can do multiple exposure. We have experienced few 
hardships with reinstalling the purge hood and
ASML working to resolve that.
See you this afternoon preferable before 4 pm.

mahnaz
On 10/2/2012 7:10 PM, Edgar Peralta wrote:
> Hi all,
>
> First of all, Is the purge hood is still removed and therefore thick 
> resist is currently not allowed?
> I'm assuming that's the case as the previous e-mail said it would be 
> so until further notice.
> Any idea when this capability may be brought back?
>
> Also, for when it's available, what are the guidelines for exposing 
> such wafers on ASML?
> I would be interested to know what energy people have used and if they 
> did anything special like say multiple exposures focused at different 
> depths of the resist.
>
> Thank you for your time,
>
>
> On Fri, Sep 14, 2012 at 4:09 PM, Gary J Sosa <gsosa at stanford.edu 
> <mailto:gsosa at stanford.edu>> wrote:
>
>     Hello Stepper Users
>
>     Do not expose thick resist (3.0 microns and above) until further
>     notice.
>     Do not use 3D alignment system. 3D align will be calibrated next
>     Tuesday(9/18)
>
>     The purge/extraction hood was removed from the system again. There
>     is some unusual problem with the hood that we do not understand
>     yet, that is causing contamination and damage to the optical
>     surfaces on the wafer table and fiducial plates. To avoid any
>     further damage, it was decided by ASML to remove the purge hood.
>      The system is released for frontside align only, including zero
>     layer. The system is not available for thick resist processing and
>     3D align. The 3D alignment system will be calibrated next Tuesday(
>     9/18)
>
>
>          Thanks... The Litho Team
>
>
>
>
> -- 
> *Edgar A. Peralta *
> /Ph.D. Candidate, /Stanford University
> Department of Applied Physics
> *M*: 954.940.2700 <tel:954.940.2700>
>

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From artyjamo at gmail.com  Tue Oct  9 16:49:34 2012
From: artyjamo at gmail.com (Aleta Jamora)
Date: Tue, 9 Oct 2012 16:49:34 -0700
Subject: released reservation @ 17:00
Message-ID: <CADrJ5+P7XEzdz-mkUhMN=Xhe5kdrvksHNJjtrsuo+FBJ38Vxjw@mail.gmail.com>

was able to get work done earlier
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From haemmerl at stanford.edu  Wed Oct 24 17:20:07 2012
From: haemmerl at stanford.edu (Alexandre Haemmerli)
Date: Wed, 24 Oct 2012 17:20:07 -0700
Subject: 5:30pm reservation released: wafers not ready
Message-ID: <DDB5BDBC-2283-449E-B57B-7C51EAE296F4@stanford.edu>





From mahnaz at stanford.edu  Thu Oct 25 10:46:09 2012
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Thu, 25 Oct 2012 10:46:09 -0700
Subject: Purge hood
Message-ID: <50897AE1.8020509@stanford.edu>

Hello all,

Asml is scheduled for purge hood instal on 10/30 and 10/31.
The upgrade might take till 4 pm on both days.

Asml FSE will do their best to calibrate the 3D  during the two days 
mentioned as well.

mahnaz




From jaypark at stanford.edu  Wed Oct 31 17:26:24 2012
From: jaypark at stanford.edu (Jason Parker)
Date: Wed, 31 Oct 2012 17:26:24 -0700 (PDT)
Subject: [asml] Thu 10am-11am released
Message-ID: <968551613.932019.1351729584044.JavaMail.root@stanford.edu>

Won't have all lots of wafers ready so releasing part of my time. 10am-11am free on Thursday, Nov 1.

Jason