HotJobs submission for 23475, Equipment Engineering Maintenance Manager
vernonbehrens at yahoo.com
vernonbehrens at yahoo.com
Tue Apr 10 07:38:54 PDT 2007
Vernon Behrens applied to the following job: Job ID: 23475, Equipment Engineering Maintenance Manager on HotJobs.com.
I have worked for Applied Materials over nine years and in the RTP division from its beginning. I was always selected lead on the most difficult projects for R&D, release and implementation to Intel. This included 200mm and 300mm RTP and the new Laser light knife project. I did all first in fab installs world wide, established I&W standards for the division. I developed the AMAT Copy exact program for Intel and was final review for all documentation releases.
At Kokusai Electric vertical furnace , I was responsible for developing the training, documentation and Copy Exact program. I hired, trained and managed all new Field service personnel.
I also developed the customer training program and trained the customer base ( mostly Intel, TI and VLSI)
I am looking for similar challenges in my next endeavor.
Name: Vernon Behrens
Address: 5335 Fairway DR
San Jose, CA 95127
Job Title: Design for service engineer
Will Relocate? Y
Work Auth: United States
Primary Phone: 408 563 4858
Secondary Phone:408 254 2434
Email: vernonbehrens at yahoo.com
Minimum Annual Salary Requirement: Unspecified
H (408) 254 2434 5335 Fairway Drive San Jose Ca 95127 Cell (408)
vernonbehrens at yahoo.com
TOTAL PRODUCT SUPPORT MANAGER
Tenacious TPS Manager with 10+ years extensive manufacturing experience in the
competitive semiconductor equipment arena. Background includes High Energy
Implanters, LPCVD, Vertical Diffusion Furnaces, Epitaxial, Etchers, and 6m x 6m
IJP for Flat Panel Display. Expertise also includes WW TPS, Copy Exact, DFS and
Project Management. Consistently succeed when given the impossible.
Litrex Corporation, Pleasanton, CA
May 2005 - present
Total Product Support Manager
Managed¨ the world-wide¨ TPS IJP team for Legacy and Gen6-series IJP tools.¨
Developed training program for TPS engineers and customer base. Responsible for
tool manufacturing, final assembly, troubleshooting and customer final test.
Instituted company procedures data base. Managed local and remote spares
âManaged Engineering Software and TPS departments for the first customer build
IJP for 3 m x 3 m flat panel displays. First tool sold to AUO for $3,700,000
orders for 8 â 12 tools.
âDirected manufacturing¨ build schedule which resulted in a 6 week reduction
Legacy build cycle.
âManaged an eight person, cross-functional, on-site team during IJP install at
Taiwan. Completed first install of IJP for flat panel displays in ~ 2.5
âInstituted changes to the BOM improving part identification in the field.
downtime and support was reduced by 50%.
Applied Materials, Santa Clara, CA
May 1992 - May 2005¨
DFS Engineer â contract (2003-2005)
Investigated new and existing AMAT tool designs for safety, ergonomics and
preventive maintenance performance..
âProvided design improvement recommendations. Lowered cost of ownership (CoO)
for customer base and reduced start-up costs for Applied and customers.
Project Manager Light Knife Project (2002-2003)
Supported hardware development of next generation RTP (rapid thermal anneal
process) semi-conductor equipment. Interfaced with Software and Hardware
âReceived patent for Dynamic Surface Anneal.
Project Manager 300 mm Project (2001-2002)
Responsible for the development of the Intel 300 mm and the integration of first
factory interface wafer automation unit to the AMAT standard 300 mm mainframe.
Managed development and integration of new 300 mm RTP chamber to mainframe.
Managed Intel Customer Demo, data report summary and presentation addressing
customer issues. Received award from the customer and AMAT.
âCreated hardware and software development leading to the quickest tool
in AMAT division history.
âManaged Field Service Install team for 200 mm RTP tools. Reduced install
$300,000 to $120,000 in 200+ installations.
âManaged development of Applied Materialâs first 300mm RTP Demo tool leading
the first customer order by Intel of over 100 tools at $3,000,000 each.
Intel Account TPS/âCopy Exactâ Manager (1997 - 2001)
Responsible for WW TPS engineers, work load scheduling, budgeting and locale
assignments. Reduced start-up costs by 65%, which set division standards for
installation costs. Developed and improved manufacturing Final Test system test
procedures. Coordinated interface between mechanical engineering, software
engineering and manufacturing to isolate and resolve system issues.
âDeveloped corporate âcopy exactâ standards to meet Intel requirements.
product reliability improving uptime by 25%.
âDeveloped 300mm corporate âcopy exactâ program for outsource vendors.
âcopy exactâ violations by 300%.
âDelivered first 300mm tool to Intel. Managed âcopy exactâ tool build that
market to 200+ orders. AMAT is still vendor for all 1256 and 1258 orders.
Customer Support Engineer (1995-1997)
Kokusai Electric Corp, Milpitas, CA
May 1992 â May 1995 Training Manager/Field Engineer
Established VLSIâs requirements which led to the first vertical furnace sold
in the American market. Key interface during Intel negotiations. Established
tool design standards criteria for the American market resulting in Kokusai
becoming the leading supplier for Intel vertical furnaces. Received award bonus
âOrganized spares support program to meet Intel order requirements for
vertical furnace. Program led to a first order of 35 tools.
âSupported initial Intel order by hiring, training, and managing entire Field
department in less than 3 months. Customer satisfaction led to a 2nd order of
50 tools at
âSaved ~6 days of downtime and $500,000 in quartz replacement parts through
consecutive power outages of customerâs semiconductor vertical furnace.
âDeveloped vertical diffusion and LPCVD furnace sectionalized training program
Intel. Training program was turned into a product and sold to entire customer
Field Engineer, Lam Research (EPI Division)
Engineering Manager, Eaton Nova (Ion Beam Division)
âDesigned new wafer clamping mechanism for semiconductor high energy
implanters at IBM, Intel and Fairchild. Reduced wafer breakage by 60% and
downtime by 45%.
B.S. Mechanical Engineering, Northeastern University, Boston, MA
B.S. Management, University of Massachusetts, Boston, MA
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