Announcement of technical seminar from Fujitu

Keizaburo Yoshie yoshie at cis.Stanford.EDU
Fri Dec 8 14:05:20 PST 2000


Date&time:Dec.14th (Thursday) 16:30-17:30
Place: CIS 101
Title: "A 0.11?m CMOS Technology with Copper and Very-low-k Interconnects for High-Performance System-On-a Chip" 
Presenter: Mr. Yoshihiro Takao ( Fujitsu limited , Japan)

Mr Yoshihiro Takao from Fujitu Japan will present Fujitsu's latest CMOS technology with Cu/VLK interconnects. He will present this topics at iedm conference at San Francisco,too. However he will give us more details , especally for fabrication process of Cu/Low interconnect and some other Key Processes on their technology  at this seminar as follows,

16:30 to 17:10 (40 min presentation )
17:10 to 17:30 ( Q&A )

Mr Yoshihiko Takao has worked for CMOS technology at least for 8 years as leader of integration team  in Fujitsu. He accomplished CMOS technology for 0.18um generation ( this technology has been used for fujitsu's production. In this technology , Cu (6 layers ) with FSG is used for interconnects. ) . After accomplishing of 0.18um generation, He has started for the development of 0.11um to 0.13um generation with his team. In the generation, 8 layers metallization with Low-K material ( SOG type) are used in order to improved perfomance.

If you are interested in this seminar, Please come and join it.

Keizaburo Yoshie 
( Visiting Scholar from Fujitsu )


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