Reminder:Announcement of technical seminar from Hitachi]

shima a-shima at fa2.so-net.ne.jp
Wed May 2 04:28:01 PDT 2001


This seminar is on tomorrow.
Hope to see you there.

Akio  Shima
Stanford University CIS   Room#110 (Visiting Scientist from  Device Development Center, Hitachi, Ltd. Japan)

shima at cis.stanford.edu   (English)
a-shima at ddc.hitachi.co.jp  (English& Japanese)
Tel: 650-725-6811
Fax:650-725-0991
420 Via Palou Mall
Stanford,CA 94305-4070



-----Original Message-----
From:	Akio Shima [SMTP:shima at cis.Stanford.EDU]
Sent:	Monday, April 23, 2001 1:01 PM
To:	cis-students at cis.Stanford.EDU; ICL Students; kovacslab at thrash.stanford.edu; kstudents at cis.Stanford.EDU; mhstudents at chroma.stanford.edu; plumbers at cis.Stanford.EDU; smirc at smirc.stanford.edu;
tstudents at kailas.stanford.edu; wonggroup at holst.stanford.edu; wooley-students at par.stanford.edu; labmembers at snf.stanford.edu
Cc:	'j-nogu at ddc.hitachi.co.jp'; 'Krishna Saraswat'; 'Simon Wong'
Subject:	Announcement of technical seminar from Hitachi

 

I would like to invite you to this special seminar.
Date&time:May.3rd (Thursday) 16:15-
Place: CIS 101
Title: " Impact of Low-K Dielectrics and barrier Metals on TDDB Lifetime of Cu Interconnects"
By: Mr. Junji Noguchi, Device Development Center, Hitachi, Ltd. Japan

Mr. Junji Noguchi from Hitachi, Ltd.  Japan will present his latest research about Cu/Low-K interconnects reliability. 
He will present this topics at IRPS 2001 at Orland, Florida.
His research about the same topic was also accepted in the last IRPS 2000 (held at San Jose, last May), so he can also introduce it to you there.    

Hope to see you there.
Akio  Shima
Stanford University CIS   Room#110 (Visiting Scientist from  Device Development Center, Hitachi, Ltd. Japan)

shima at cis.stanford.edu   (English)
a-shima at ddc.hitachi.co.jp  (English& Japanese)
Tel: 650-725-6811
Fax:650-725-0991
420 Via Palou Mall
            Stanford,CA 94305-4070



Biography:
Mr.Junji Noguchi received the B.S. (1994) and the M.S. (1996) in electrical
engineering from Shibaura Institute of Technology, Japan. In 1996 he joined
Device Development Center, Hitachi Ltd., Tokyo, Japan, where he has been
developing the multilevel metallization process technology for high speed
devices, especially for metallization and reliability of copper interconnects.

Title: 
" Impact of Low-K Dielectrics and barrier Metals on TDDB Lifetime of Cu Interconnects" (To be presented at IRPS 2001, Orland, Florida)
Abstracts: 
Time-dependent dielectric breakdown (TDDB) in Cu metallization and the dependence on the presence of barrier metal, barrier metal thickness, the kind of barrier metals and the Low-K dielectrics, is
investigated.
There is a distinct difference in TDDB degradation mechanism with and without barrier metals. TDDB degradation of Cu interconnects without and with barrier metal is caused by bulk mode and CMP-surface
mode, respectively. TDDB characteristics with barrier metal is almost the same for different barrier metal thickness and depends much more strongly on the electric field strength than the MIS
structure. Additionally, both degradations, related to Cu-ion diffusion, are mainly caused not by thermal stress but by electrical stress. The barrier properties of Ta and TaN are better than those of
TiN against Cu-ion diffusion into dielectrics, for TDDB.
In the case of Low-K structure, TDDB property with barrier metal also depends on the CMP-surface. With Low-K dielectrics the electric field strength is concentrated near the CMP-surface and the TDDB
lifetime reduces as K-value becomes lower. However, all low-K structure in this study are able to satisfy the 10-year TDDB reliability specifications for the capacitor.
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