PEUG Mtg on Deep Si Etching, Thursday

Jim McVittie mcvittie at cis.Stanford.EDU
Wed May 9 09:13:47 PDT 2001

SNF Lab Members,

I am chairing a Plasma Etch User Group meeting on MEMS related plasma
etching tomorrow afternoon. The mtg is free and opening to anyone who
wants to attend. The mtg is at the National Semiconductor Credit
Union Auditorium in Santa Clara. See details below. There will be three
talks on deep silicon etching. Cookies are served at 2:00 with the talks
starting at 2:30. All the talks should be finished by 4:30. There should 
be a number of people going from Stanford. If you need a ride, let me know
and I will see if I help.  

James P. McVittie	                Senior Research Scientist
Allen Center for Integrated Systems     jmcvittie at
Stanford University             	Tel: (650) 725-3640	
Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
Stanford, CA 94305-4075	

> ******************* PLASMA ETCH USERS GROUP **********
> of the Northern California Chapter of the AVS
> ********************************************************
> May 2001 MEETING
> Topic:  MEMS Related Plasma Etching
> Date:   Thursday, May 10, 2001
> Time:   2:00 - 5:00 pm
> Place:  National Semiconductor Credit Union Auditorium
>              955 Kifer Rd.
>              Santa Clara, CA 95051
> Directions to the National Semiconductor Credit Union Auditorium:
> >From 101: Go south on Lawrence Expressway. Turn right on Kifer Rd. 
> Turn right into the driveway of the National Semiconductor Credit Union
> (955 Kifer Rd.) and find parking in the Credit Union parking lot. The
> auditorium is on the west side of the building and can be entered from the
> door in the rear next to the company park.
> >From 280: Go north on Lawrence Expressway. Turn left on Kifer Rd. 
> Follow directions above.
> ****************************************************
> See a map:
> ****************************************************
> Agenda: 2:00 - 2:30 Refreshments
>          2:30 - 4:00 Presentations
> Chair: Jim McVittie, mcvittie at cis.Stanford.EDU
> Speakers:
> ---------------
> Deep Reactive Ion Etching (DRIE) for Multi-Wafer Projects
> Arturo Ayon
> Sony Semiconductor
> 1 Sony Place
> San Antonio, TX 78245-2100
> We review the physics and the performance of a DRIE tool, the influence of
> etching variables on anisotropy, uniformity, silicon etching rate,
> selectivity and scalloping. We discuss the charging effects observed on
> high aspect ratio structures when employing SOI substrates, the dependance
> of the footing effect on etching conditions, and the utilization of the
> local electric fields generated when reaching a dielectric stop layer for
> achieving ion flux steering.
> The utilization of deep reactive ion etching (DRIE) in conjunction with
> wafer bonding schemes makes possible the micromanufacturing of complex
> 3-dimensional structures at a microscale level, in a manner not previously
> practical and in some cases unattainable. Plasma etching methods, in
> general, limit the geometry to extruded 2D prismatic shapes. However, DRIE
> in combination with wafer bonding techniques offers to designers the
> flexibility not available to the previous generation of technologists.
> These techniques have been successfully applied in the microfabrication of
> a large variety of structures including bipropellant silicon
> micro-rockets, heat exchangers, turbo chargers and micro-combustors.
> ______________
> Low Frequency Deep Reactive Ion Etching for SOI Processing
> Matthew Wasilik
> Berkeley Sensor & Actuator Center
> 497 Cory Hall
> Berkeley, CA 94720-1770
> Due to the inherently non-uniform etching effects in the standard DRIE
> process, a new technique has been developed specifically for SOI (Silicon
> On Insulator) etching.In short, a separate pulsed, low frequency power
> input is applied to the platen during the etching cycle. This essentially
> allows ions to escape more readily from deep trenches when the etching
> cycle is done. From this a decrease in over-etch sensitivity emerges, and
> the notching or ^footing^ of Silicon structures is minimized. The end
> result is the ability to produce high quality large aspect ratio
> structures. 
> ______________
> Advanced Deep Silicon Etching for Deep Trench Isolation, Optical
> Components
> and Micro-Machining Applications
> Padmapani Nallan, Anisul Khan, Sharma Pamarthy, Shu-Ting Hsu, Ajay Kumar
> Applied Materials
> 3320 Scott Boulevard
> Santa Clara, CA 95054
> Traditionally, deep silicon etching has been used for DRAM capacitor
> trenches and deep trench isolation applications for BiCMOS devices.
> Recently, we have seen a plethora of new applications requiring deep
> silicon etching (thru wafer etches for inkjet applications and optical
> fiber alignment, microsensors and actuators etc.). The etch requirements
> for all these applications are as diverse as the applications themselves.
> The CDs range from sub-micon to millimeter sizes and the etch depths range
> from a 1-2um to through wafer (~700um for a six inch wafer).  Some
> applications such as waveguides require very smooth sidewall (typical
> requirement is <4nm surface roughness to avoid light scattering), while
> through wafer etches require very high etch rates (>10um/min) with very
> high selectivity to resist and hardmask (typically >70:1). These varied
> applications with a wide range of etch requirements have motivated us to
> develop a portfolio of processes, in the DPS-DT chamber, which cater to
> different application needs. We have used two different approaches to
> develop processes that satisfy the requirements of the different
> applications. One is a single step approach where we use a SF6/HBr/O-2 or
> a SF6/C4F8 chemistry to etch the trenches. This approach is necessary for
> applications where smooth sidewalls are required. An SF6 based etch
> chemistry was chosen to get high etch rates.  The other is the Time
> Multiplex Gas Modulation (TMGM)  approach, where we have a sequence of
> short deposition and etch steps cycled many times over to get the required
> etch depth. This approach gives a high etch rate with very high
> selectivity to both oxide and resist.  The capabilities of our tool with
> all these processes will be presented.
> _____________________________
> Della Miller
> AVS West
> 1265 El Camino Real, Ste. 109
> Santa Clara CA 95050
> Phone:   408-246-3600
> Fax:       408-246-7700
> E-mail:   della at
> Web:

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