From niblock at analatom.com Thu Nov 1 17:47:04 2001 From: niblock at analatom.com (Trevor Niblock) Date: Thu, 1 Nov 2001 17:47:04 -0800 Subject: Missing boxes Message-ID: Hi, I'm working for Analatom at SNF and some of our stuff have gone missing. In particular two larger boxes, one blue and one clear and also a couple wafer boxes with SOI wafers. They were in the far right corner of the cleanroom relative to the entrance. The larger boxes contained masks and wafers. They are plastic and aprox 10" deep, 12" high and 16" across. They were marked Analatom and dated 10/03/01. If anyone has moved or seen them could you please email me as we need to find them. many thanks Trevor. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is confidential. It may also be privileged or protected by other legal rules. It does not constitute an offer or acceptance of an offer, nor shall it form any part of a legally binding contract. If you have received this communication in error, please let us know by reply then destroy it. You should not use, print, copy the message or disclose its contents to anyone. E-mail is subject to possible data corruption, is not secure, and its content does not necessarily represent the opinion of this Company. No representation or warranty is made as to the accuracy or completeness of the information and no liability can be accepted for any loss arising from its use. This e-mail and any attachments are not guaranteed to be free from so-called computer viruses and it is recommended that you check for such viruses before down-loading it to your computer equipment. This Company has no control over other websites to which there may be hypertext links and no liability can be accepted in relation to those sites. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * -------------- next part -------------- A non-text attachment was scrubbed... Name: Trevor Niblock.vcf Type: text/x-vcard Size: 568 bytes Desc: not available URL: From plummer at ee.stanford.edu Fri Nov 2 06:53:21 2001 From: plummer at ee.stanford.edu (Jim Plummer) Date: Fri, 2 Nov 2001 06:53:21 -0800 Subject: New SNF Industrial Affiliates Program Message-ID: Labmembers: As you are all well aware, SNF is an unusual and remarkable resource; it is a high tech "sandbox", made openly available to industrial, as well as academic researchers. Over the past several years, SNF has seen a tremendous growth in lab membership and in the number and diversity of research projects. Lab use has nearly doubled over the past three years. The most recent months have set all time records for lab use and revenues from lab fees. The two sources of support which sustain the SNF are lab fees which come from lab use, and the NSF NNUN contract which supports not just the SNF but also the other four university labs which are part of the NNUN. To first order, lab fees and the NSF contract each provide about half of the annual operating budget for the SNF. Both of these sources of funds are quite restricted in how they can be used. The NSF contract is a federal government contract and in many cases the user fees paid monthly also come from individual PI government contracts. Thus both sources of support for the SNF are "restricted" by all of the policies that govern federal contracts. There are many situations in which a more flexible source of funds supporting the SNF would provide great benefit to all lab members. Examples include: o the ability to quickly react to modest capital equipment purchase needs and opportunities to upgrade the lab; o providing a source of funds for non-salary compensation (overtime or bonuses) as performance incentives or to reward staff; o covering bad debts in the rare cases when industrial users do not pay their bills (if a startup goes out of business, for example). Most faculty running large research programs have flexible unrestricted accounts that they can use for these and other similar purposes. The sources of these funds are most often gifts that come to individual faculty or to research centers. The SNF at present does not have such an account. To address these issues, I am announcing a new initiative: the SNF Industrial Affiliates Program. This program will fund an "unrestricted" account, which because of the nature of the funding source, is not subject to the constraints described above. This will allow us the flexibility to act on opportunities (such as equipment acquisitions), respond to problems (such as those requiring staff overtime), and provide insurance for continued open operation in these uncertain economic times. We are asking all the industrial organizations who use the SNF to support us by joining the SNF Industrial Affiliates Program. A description of this program is attached. Although participation in the Program is entirely voluntary, the fee is nominal ($2.5K per year), particularly when compared to the value that SNF provides to our industrial labmembers. Over 100 companies made use of SNF during the last calendar year; if every industrial organization participates, the SNF will have significant flexibility in responding to future needs and opportunities. I ask that every industrial labmember help us by encouraging your companies to participate in this program and by providing the appropriate corporate contact information to the SNF staff. The SNF is a dynamic and diverse community of researchers. All lanmenbers will benefit in a significant way if this new program is successful. Thanks for your help. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: SNF_Affiliates_Program.doc Type: application/msword Size: 22016 bytes Desc: not available URL: From mahnaz at snf.stanford.edu Fri Nov 2 15:28:32 2001 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Fri, 02 Nov 2001 15:28:32 -0800 Subject: How bad are we getting Message-ID: <3BE32C20.5909F479@snf.stanford.edu> To all the members, This afternoon I found few samples on the wipes left on the hot plate at 120o C. The wipes started turning brown and another lab member notified me, well guess where the samples are? Come and see me .... be brave and take responsibility for your action. To all the users this is totally unacceptable. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From caudillomalik at netscape.net Fri Nov 2 18:14:19 2001 From: caudillomalik at netscape.net (David Caudillo) Date: Fri, 02 Nov 2001 21:14:19 -0500 Subject: ~Fri 18:00_No Di Water Message-ID: <08BB9CDD.65CA353A.0DC3DFDB@netscape.net> John Shott is currently investigating problem at the DI Pad -- David Caudillo __________________________________________________________________ Your favorite stores, helpful shopping tools and great gift ideas. Experience the convenience of buying online with Shop at Netscape! http://shopnow.netscape.com/ Get your own FREE, personal Netscape Mail account today at http://webmail.netscape.com/ From caudillomalik at netscape.net Fri Nov 2 18:37:12 2001 From: caudillomalik at netscape.net (David Caudillo) Date: Fri, 02 Nov 2001 21:37:12 -0500 Subject: DI WATER PROBLEM Message-ID: <5703882A.19561FCC.0DC3DFDB@netscape.net> The di water tank out at the di pad is low. It needs to replenish. Please Do Not Use the di water at any station during this time period. There may be a problem with the di water recovery system so beware. -- David Caudillo __________________________________________________________________ Your favorite stores, helpful shopping tools and great gift ideas. Experience the convenience of buying online with Shop at Netscape! http://shopnow.netscape.com/ Get your own FREE, personal Netscape Mail account today at http://webmail.netscape.com/ From shott at snf.stanford.edu Fri Nov 2 21:11:04 2001 From: shott at snf.stanford.edu (John Shott) Date: Fri, 02 Nov 2001 21:11:04 -0800 Subject: DI Water outage ... Friday evening update. Message-ID: <3BE37C68.A0D223D1@snf.stanford.edu> SNF Labmembers and CISX Lab Occupants: There appears to be a significant DI water leak or water flow condition that has drained the DI system to the point that the pumps shutoff to protect themselves. Thus far, however, we have been unable to find a leak in the system or a sink that was left on that can be viewed as the source of the problem. At the moment, the pumps that circulate the water through CIS-X and through SNF are both off. It is our belief, based on water loss rates with either set of pumps turned on, that the leak appears to be in the CIS-X half of the loop. This conclusion is by no means definitive, but it is the best that we can determine at this point. As of 9 p.m. there is no DI water in either CIS-X or SNF. The Reverse Osmosis system is working as fast as it can to refill the tank. Once the tank is partially refilled, the SNF pumps may be able to be turned on for very limited use ... however, if the usage is sufficiently great that the tank does not continue to fill, the entire system will be shut off until we have substantial recovery. At this point, I believe that there will not be useable levels of water until at least midnight. To avoid processing frustration, I would recommend not counting on DI water until Saturday morning. As soon as we have any further information related to DI water in either half of the building, we will let you know ... Thanks, John Shott, Jim Haydon, and Eric P. From shott at snf.stanford.edu Sat Nov 3 10:04:43 2001 From: shott at snf.stanford.edu (John Shott) Date: Sat, 03 Nov 2001 10:04:43 -0800 Subject: DI water update: SNF operational, CIS-X still off-line Message-ID: <3BE431BB.29A72593@snf.stanford.edu> SNF Labmembers and CIS-X lab occupants: Last night Jim Haydon and Eric Perozziello made some measurements that seem to confirm the the leak in the DI water system is in the CIS-X half of the system, that it results in DI water ending up in the acid waste neutralization system, and that it results in a major loss of water: likely 20-25 GPM! Last night, they left the CIS-X recirculating pumps off and the SNF pumps on. As of this morning, the storage tank has recovered to slightly more than 50% of full capacity. This is further confirmation that the leak in in the CIS-X half of the building because the storage tank level falls continuously ONLY when the CIS-X pumps are on (despite the Reverse Osmosis sytem refilling the system at approximately 12 GPM). Accordingly the SNF lab should be fully operational today. Please, however, do not waste water. CIS-X labs will not have DI water until further notice. When there are sufficient people to checkout all possible sources, the pumps can be turned on for a short time in order to find the leak. (One would think that a 20-25 GPM loss of water should be easy to find ... anyone with better local knowledge of the DI water system in CIS-X is welcome to help find the problem area.) However, it cannot be left on continuously until the water loss is found ... at the present rate of loss, the current amount of stored water would be depleted in about 8 hours. Thanks for your cooperation, John From yjlin at stanford.edu Mon Nov 5 12:23:19 2001 From: yjlin at stanford.edu (Yu-Ju Lin) Date: Mon, 5 Nov 2001 12:23:19 -0800 (PST) Subject: Shallow Si etch(2um) with Drytek2 Message-ID: Hi all, I wonder how uniform is the shallow Si etch with Drytek2, could that be as good as 20% error? Since I must use photoresist as an etch mask, I couldn't use Lampoly. And with STS, the etch rate is too fast; uniformity is also worse. My process will be six trenches, 10um wide, 2um deep, and smallest spacing is 5um. Thanks!! Yu-ju From jhaydon at snf.stanford.edu Mon Nov 5 12:26:33 2001 From: jhaydon at snf.stanford.edu (Jim Haydon) Date: Mon, 05 Nov 2001 12:26:33 -0800 Subject: DI water now back on line Message-ID: <3BE6F5F9.50878769@snf.stanford.edu> To CISX occupants: The cause of the DI water loss to your building has been identified and fixed. The drain line one one of the DI column bottles was inadvertently left open causing a loss of water of about 25 GPM. The normal Loss rate is about 1 GPM. Jim Haydon From mtang at snf.stanford.edu Tue Nov 6 11:18:36 2001 From: mtang at snf.stanford.edu (Mary Tang) Date: Tue, 06 Nov 2001 11:18:36 -0800 Subject: Labmembers' Mtg Minutes Message-ID: <3BE8378C.60C88404@snf.stanford.edu> Hi all -- The summary of the Labmembers' meeting on Nov. 1 is now available at: http://snf.stanford.edu/Labmembers/MtgNov1.html Just so you know, included in these minutes are: 1. The rev. 0 holiday shutdown schedule for the lab (so you can plan your processing accordingly!) 2. Rules for lab storage and initial plans for a mega-lab cleanup program. Includes the announcement that: ALL PERSONAL ITEMS NEED TO BE REMOVED FROM THE LAB BY DEC 17. (Did I get your attention? I promise, more details to follow.) 3. Summary of an open discussion on reservations policies. Questions, comments, suggestion are appreciated. Thanks, Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From yjlin at stanford.edu Thu Nov 8 20:17:45 2001 From: yjlin at stanford.edu (Yu-Ju Lin) Date: Thu, 8 Nov 2001 20:17:45 -0800 (PST) Subject: diffusion barrier for Cu on Si Message-ID: Hi all, I wonder if anybody is processing Cu on Si? I would like to know the diffusion barrier for that. Is the Cu diffusion into SiO2 also comparable to that into Si? Thanks! Yu-ju From fshi at SLAC.Stanford.EDU Thu Nov 8 21:09:28 2001 From: fshi at SLAC.Stanford.EDU (Shi, Frank F.) Date: Thu, 08 Nov 2001 21:09:28 -0800 Subject: diffusion barrier for Cu on Si Message-ID: Typically one can use Ta or TaN as barrier layers. But I don't think CIS can do Ta or TaN, can they? Good luck. -----Original Message----- From: Yu-Ju Lin [mailto:yjlin at Stanford.EDU] Sent: Thursday, November 08, 2001 8:18 PM To: labmembers at snf.stanford.edu Subject: diffusion barrier for Cu on Si Hi all, I wonder if anybody is processing Cu on Si? I would like to know the diffusion barrier for that. Is the Cu diffusion into SiO2 also comparable to that into Si? Thanks! Yu-ju From guerra at par.stanford.edu Fri Nov 9 13:30:11 2001 From: guerra at par.stanford.edu (Ann Guerra) Date: Fri, 9 Nov 2001 13:30:11 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 11/13/01 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Offset Reduction Techniques for the Design of Accurate Untrimmed CMOS Bandgap Reference Circuits" Vijay Ceekala National Semiconductor Wired Communication Division, Santa Clara, CA Tuesday, November 13, 2001 4:15 p.m. Building 380, Room 380X ABSTRACT: Bandgap based reference circuits are an important class of building blocks, widely used in almost all signal processing/communication chips and systems. These are most commonly used for providing constant reference voltage that has a well defined magnitude, and minimal variation over process, voltage and temperature. CMOS based reference circuits, however, are highly prone to random mismatches of the MOS transistors. This presentation will present design techniques to reduce the effect of these random mismatches. BIO Education: BSEE from SVU college of Engineering, Tirupati, India.,(1993) MSEE from University of South Florida, Tampa, Florida.,(1995) Work Experience: Senior Circuit Designer in National Semiconductor's Wired Communications Division since 1995. Responsible for development of mixed signal circuits used in networking products. Publications: * A new type of programmable pulse generator..IEEE Student Charter, New Delhi, India.(1993.February.Best paper Award). * Device performance characterization and Junction mechanisms in CdTe/CdS solar cells (Solar Ebergy Materials and Solar Cells, 58(4), 1999) * Recent Advances in Thin Film CdTe Solar cells (AIP Conference Proceedings, (353), 1996) * A method for reducing the effects of random mismatch in CMOS Bandgap references (To be presented at ISSCC 2002) Patents: 2 issued patents Current Interests: *Bandgap reference circuits *Timing recovery techniques and circuits From rcrane at snf.stanford.edu Fri Nov 9 15:35:12 2001 From: rcrane at snf.stanford.edu (Dick Crane) Date: Fri, 09 Nov 2001 15:35:12 -0800 Subject: Surplus Aligners Message-ID: <3BEC6830.82138C75@snf.stanford.edu> SNF is offering for sale a portion of its fine stock of mature alignment equipment. We have two Kasper 2001, contact aligners, state-of-the-art in the early '70s, and one Canon PLA-501FA contact/proximity aligner with autofeed. Excellent for start-ups in the MEMS and/or photonics fields. The aligners are 3 & 4 inch capable and appear to be possessing all of their vital components. Make an offer today and avoid the end-of-the-month rush. For answers concerning questions about the aligners contact: Dick Crane Operations Manager Stanford Nanofabrication Facility rcrane at stanford.edu 650 725-3665 From ug-s at rpl.stanford.edu Thu Nov 15 02:39:46 2001 From: ug-s at rpl.stanford.edu (Yuji SAITO) Date: Thu, 15 Nov 2001 02:39:46 -0800 Subject: Zirconia deposition outsources Message-ID: <4.3.2-J.20011115023943.0382d428@smtp.mindspring.com> Dear labmembers, Does anyone have information about companies which will do zirconium oxide deposition for general customers? RF-sputtering would be fine for my purpose. Please send me emails if you have this. Regards, -Yuji From yjlin at stanford.edu Fri Nov 16 11:22:54 2001 From: yjlin at stanford.edu (Yu-Ju Lin) Date: Fri, 16 Nov 2001 11:22:54 -0800 (PST) Subject: 2 mil Au wire for bonding Message-ID: Hi all, I wonder if anyone is using Au wire whose diameter is larger than 2 mil? I need that because I will apply large current in my device, and the wirebond will be long. So I would like to reduce the dissipated power as much as possible. Thanks a lot! Yu-ju From li-peng.wang at intel.com Sun Nov 18 10:29:18 2001 From: li-peng.wang at intel.com (Wang, Li-peng) Date: Sun, 18 Nov 2001 10:29:18 -0800 Subject: High-quality sapphire film on silicon Message-ID: <39B5C4829263D411AA93009027AE9EBB0FBBE1AD@FMSMSX35> Dear labmembers, Does anyone have information about companies which sale high-quality single-crystal (001)a-Al2O3 (sapphire) films on silicon wafers. Please send me emails if you have this. Thanks. Regards, Li-Peng From guerra at par.stanford.edu Mon Nov 19 19:26:48 2001 From: guerra at par.stanford.edu (Ann Guerra) Date: Mon, 19 Nov 2001 19:26:48 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 11/20/01 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "An Integrated 3D Ultrasonic Imaging System" Kambiz Kaviani and Omer Oralkan Stanford University Tuesday, November 20, 2001 4:15 p.m. Building 380, Room 380X ABSTRACT: Progress in semiconductor technology and specifically CMOS has made the integration of many functions in a single chip possible. Today integration of as many as one billion memory cells per chip is no longer a challenge. Technology scaling along with design creativity has served many applications which have not been practical to be feasible. Portable cellular phones, computers, GPS navigators are a few examples. On the other hand, fabrication of micro-mechanical elements like sensors and actuators along with integrated circuits on the same silicon wafer in recent years has created a new generation of integrated systems referred to as Micro-Electro-Mechanical Systems (MEMS). The importance of MEMS devices lies in the fact that they enable the realization of devices which are not possible to implement in a larger scale. Nevertheless, integration of the whole system on the same wafer or chips sounds inevitable because as device dimensions shrink the sensitivity drops as the parasitics become more significant. Merging electronics and mechanics in a single chip not only would improve the sensitivity but also makes the power dissipation and chip area consumption more efficient by eliminating the inter-chip interconnect parasitics. The objective of this work is the feasibility of implementation of an integrated three-dimensional ultrasonic imaging system using capacitor macro-machined ultrasound trasducers (cMUTs). cMUTs as the leading edge technology of choice for ultrasonic array transducers are fabricated using CMOS compatible processes and prove to have a larger dynamic range and percentage bandwidth compared to piezoelectric devices with fewer practical limitations. In this research both fundamental and practical limitations for the system are investigated and the techniques to allow the implementation are developed. In order to construct an image, a novel beamforming architecture has been proposed and the implementation of the whole system in CMOS is investigated. Since medical ultrasound imaging constrains the resolution of the signals to better than 10 bits, the implementation of dedicated front-end electronics for reading the cMUT elements information has been investigated and an analog to digital converter as the interface for the digital beamforming processing has been designed and fabricated. Pipelining along with multiplexing has been employed to make the design more efficient and practical. The pipeline architecture offers area or speed advantages over the flash or multistep approaches due to concurrent processing of the analog signal. The experimental ADC prototype has been implemented in 0.25um standard CMOS processes which achieves 10 bits of resolution for 8 ultrasound channels of 10MHz bandwidth and occupies 2mmX2mm of silicon area. The novel ADC architecture is expandable to address a greater number of channels at the cost of more area and power. From jhsim at stanford.edu Mon Nov 19 20:36:59 2001 From: jhsim at stanford.edu (Jae Hoon Sim) Date: Mon, 19 Nov 2001 20:36:59 -0800 Subject: Releasing dummy wafer after STS etching References: <39B5C4829263D411AA93009027AE9EBB0FBBE1AD@FMSMSX35> Message-ID: <003801c1717c$fe2b0480$41a00c80@Stanford.EDU> Dear labmembers, I fabricate membrane using STS etching. I etched holes almost completely through, just remianing membrane of 0.6 micron thickness. I usually attached dummy wafer to my device wafer because I etched holes almost completely through . I think that releasing dummy wafer after STS etching, causes significant damage on membrane. Does anyone know how to detach the dummy wafer without damage on membrane? Or does anyone know the way to do STS etching without dummy wafer? When STS etching is done without dummy wafer, my membrane is too thin to sustain the big pressure difference between the bottom and the top side of wafer during STS etching. Thanks, Jae Hoon Sim From dhelqaq at hotmail.com Tue Nov 20 09:26:37 2001 From: dhelqaq at hotmail.com (Deirdre Heyde Elqaq) Date: Tue, 20 Nov 2001 09:26:37 -0800 Subject: Tylan3-canceled Message-ID: I had Tylan 3 from 9am-3pm today but do not need it. Feel free to use it. dhelqaq _________________________________________________________________ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp From mahnaz at snf.stanford.edu Tue Nov 20 13:32:40 2001 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Tue, 20 Nov 2001 13:32:40 -0800 Subject: Singe Oven Message-ID: <3BFACBF8.5D68F447@snf.stanford.edu> Hello all, There are two cassette in the Singe oven which has been in there for more than a week, Please clean it up or I will by tomorrow 11/21. mahnaz From mahnaz at snf.stanford.edu Tue Nov 20 13:45:32 2001 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Tue, 20 Nov 2001 13:45:32 -0800 Subject: Mask Cleaner Message-ID: <3BFACEFC.F9E16AE5@snf.stanford.edu> Hello all, The mask cleaner is up but now is running in manual mood only. You will find the procedure attached to the system, you should be able to follow it step by step if not conformable about it ask Mike or I and we will go over it with you. I will order a timer on Monday for the system. When you stop the system do not move the mask till it comes to full stop, you will get hurt, I assure you. There will be a bout 2000 psi pressure. Mike will try to interlock the lid so will stop the mask rotation after the lid gets pushed to the side. Please see me if you are not train or used it in the past. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Wed Nov 21 23:10:51 2001 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 21 Nov 2001 23:10:51 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 11/27/01 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "A Cool Cooling Fan Controller" Jeroen Fonderie Maxim Tuesday, November 27, 2001 4:15 p.m. Building 380, Room 380X ABSTRACT Controlling the speed of cooling fans in servers, desktop computers and even notebooks increases the fan's lifetime, reduces audible noise and lowers power consumption. This presentation deals with design considerations for a fan controller that linearly regulates and monitors the fan's speed. On a system level, the feedback loop around the fan will be discussed and it will be shown that a phase-locked loop design does not work for this application. On a transistor level, several of the analog sub-circuits (opamps, comparators, a simple 10-bit DAC) will be analyzed. Bruce Wooley wrote: > Jeroen, > > Great. November 27 it is. I'll look for the title and abstract next week > or so. > > Thanks. > > Bruce From guerra at par.stanford.edu Mon Nov 26 08:46:35 2001 From: guerra at par.stanford.edu (Ann Guerra) Date: Mon, 26 Nov 2001 08:46:35 -0800 (PST) Subject: EE310 Integrated Circuits Seminar REMINDER Message-ID: EE310 Integrated Circuits Technology and Design Seminar "A Cool Cooling Fan Controller" Jeroen Fonderie Maxim Tuesday, November 27, 2001 4:15 p.m. Building 380, Room 380X ABSTRACT Controlling the speed of cooling fans in servers, desktop computers and even notebooks increases the fan's lifetime, reduces audible noise and lowers power consumption. This presentation deals with design considerations for a fan controller that linearly regulates and monitors the fan's speed. On a system level, the feedback loop around the fan will be discussed and it will be shown that a phase-locked loop design does not work for this application. On a transistor level, several of the analog sub-circuits (opamps, comparators, a simple 10-bit DAC) will be analyzed. From l.fama at bioprocessors.com Thu Nov 29 13:56:07 2001 From: l.fama at bioprocessors.com (Larry Fama) Date: Thu, 29 Nov 2001 13:56:07 -0800 Subject: Heater Message-ID: <001301c17920$a72aa9f0$0300a8c0@larry> Has anyone any experience using Ti/Pt or Indium-Tin-Oxide on quartz or Si to form a heating element? I'm looking for any insights or problems associated with the fabrication. Larry Fama Bioprocessors 1900 Addison Street Mezzanine Berkeley, CA 94704 510 883 0129 883 0175 FAX 650 224 2306 cell -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Thu Nov 29 15:50:43 2001 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 29 Nov 2001 15:50:43 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 12/4/01 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "A 5-GHz CMOS transceiver for IEEE 802.11a Wireless LAN" David Su Atheros Communications Tuesday, January , 2000 4:15 p.m. Building 380, Room 380X ABSTRACT High-speed wireless communications at 5-GHz, as specified by the IEEE 802.11a Wireless LAN protocol, can provide data rates of up to 54 Mbps. This talk describes the design of the RF and analog baseband functions of a Wireless LAN. The transceiver consists of a transmitter, a receiver, a frequency synthesizer, biasing circuitry, and control logic. The transmitter, with an on-chip power amplifier, has a maximum output power of 22 dBm. The receiver with on-chip LNA and programmable baseband amplifiers, has an overall noise figure of 8dB. The frequency synthesizer has a phase noise of -112dBc/Hz at 1MHz offset. The transceiver is implemented in a 0.25um CMOS technology with a die area of 22 sq mm. It has also been incorporated into a radio system to form a high-speed, IEEE 802.11a-compliant wireless LAN. From guerra at par.stanford.edu Thu Nov 29 15:58:06 2001 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 29 Nov 2001 15:58:06 -0800 (PST) Subject: (corrected) EE310 Integrated Circuits Seminar, 12/4/01 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "A 5-GHz CMOS transceiver for IEEE 802.11a Wireless LAN" David Su Atheros Communications Tuesday, December 4, 2001 4:15 p.m. Building 380, Room 380X ABSTRACT High-speed wireless communications at 5-GHz, as specified by the IEEE 802.11a Wireless LAN protocol, can provide data rates of up to 54 Mbps. This talk describes the design of the RF and analog baseband functions of a Wireless LAN. The transceiver consists of a transmitter, a receiver, a frequency synthesizer, biasing circuitry, and control logic. The transmitter, with an on-chip power amplifier, has a maximum output power of 22 dBm. The receiver with on-chip LNA and programmable baseband amplifiers, has an overall noise figure of 8dB. The frequency synthesizer has a phase noise of -112dBc/Hz at 1MHz offset. The transceiver is implemented in a 0.25um CMOS technology with a die area of 22 sq mm. It has also been incorporated into a radio system to form a high-speed, IEEE 802.11a-compliant wireless LAN. From shott at snf.stanford.edu Fri Nov 30 08:16:34 2001 From: shott at snf.stanford.edu (John Shott) Date: Fri, 30 Nov 2001 08:16:34 -0800 Subject: Updated version of Coral released .... Message-ID: <3C07B0E2.E427A9D1@snf.stanford.edu> SNF Lab Members: We have released a new version of Coral today ... including a new version of the Remote Client. This means that you should see that Java Web Start will download a new version of the client when you fire it up. While many of the changes are "under the covers", we believe that they will result in more reliable, more robust operation of Coral. In particular, there is better monitoring and clean up of "dead" clients as well as monitoring of server status (including automatic restart if they die). Prior to now, if the servers had to be restarted, it left a bunch of visible but non-responsive clients. These should now be cleaned up and avoid these situations where the client doesn't respond. Additionally, to try to keep overall system load under control, each lab member may only run one "in-lab" client at a time ... if you start more than one, then the previous one will be killed. (Of course, if you do what you should be doing and have a card key that you take from SunRay to SunRay, then you only do have one coral client that follows you around). As a reminder, however, you should ALWAYS have a coral session running while you are in the lab. Why? It is one of the ways that we can determine who is in the lab at any particular time ... in the event of an emergency, that can be important in helping to determine if anyone is missing. Also, people who login, enable a piece of equipment, then logout ... then login again, disable the equipment, and logout actually use more resources than someone who logs in when they enter the lab and logs out when they leave the lab. Thanks for your cooperation ... if you see problems with the new release or wish to offer comments or suggestions for future improvements to Coral, please send them to coral at snf.stanford.edu. Your Coral Development Team