EE310 Integrated Circuits Seminar, 11/13/01

Ann Guerra guerra at par.stanford.edu
Fri Nov 9 13:30:11 PST 2001


EE310 Integrated Circuits Technology and Design Seminar


 "Offset Reduction Techniques for the Design of Accurate
       Untrimmed CMOS Bandgap Reference Circuits"

                 Vijay Ceekala
             National Semiconductor
 Wired Communication Division, Santa Clara, CA

	   Tuesday, November 13, 2001
		   4:15 p.m.
	   Building 380, Room 380X



ABSTRACT:

Bandgap based reference circuits are an important class of building blocks,
widely used in almost all signal processing/communication chips and systems.
These are most commonly used for providing constant reference voltage that
has a well defined magnitude, and minimal variation over process, voltage
and temperature.

CMOS based reference circuits, however, are highly prone to random
mismatches of the MOS transistors. This presentation will present design
techniques to reduce the effect of these random mismatches.

BIO

  Education: BSEE from SVU college of Engineering, Tirupati, India.,(1993)
             MSEE from University of South Florida, Tampa, Florida.,(1995)

  Work Experience:   Senior Circuit Designer in National Semiconductor's
                     Wired Communications Division since 1995. Responsible
                     for development of mixed signal circuits used in
                     networking products.

  Publications:
              * A new type of programmable pulse generator..IEEE Student
                Charter, New Delhi, India.(1993.February.Best paper Award).

              * Device performance characterization and Junction mechanisms
                in CdTe/CdS solar cells
		(Solar Ebergy Materials and Solar Cells, 58(4), 1999)

	      * Recent Advances in Thin Film CdTe Solar cells
		(AIP Conference Proceedings, (353), 1996)

	      * A method for reducing the effects of random mismatch in CMOS
	        Bandgap references (To be presented at ISSCC 2002)


 Patents: 2 issued patents


 Current Interests: *Bandgap reference circuits
		    *Timing recovery techniques and circuits










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