EE310 Integrated Circuits Seminar, 11/20/01

Ann Guerra guerra at par.stanford.edu
Mon Nov 19 19:26:48 PST 2001


EE310 Integrated Circuits Technology and Design Seminar


  "An Integrated 3D Ultrasonic Imaging System"

	Kambiz Kaviani and Omer Oralkan
		Stanford University

	   Tuesday, November 20, 2001
		   4:15 p.m.
	   Building 380, Room 380X


		   ABSTRACT:

Progress in semiconductor technology and specifically CMOS has made the
integration of many functions in a single chip possible. Today integration
of as many as one billion memory cells per chip is no longer a challenge.
Technology scaling along with design creativity has served many applications
which have not been practical to be feasible. Portable cellular phones,
computers, GPS navigators are a few examples. On the other hand, fabrication
of micro-mechanical elements like sensors and actuators along with
integrated circuits on the same silicon wafer in recent years has created a
new generation of integrated systems referred to as Micro-Electro-Mechanical
Systems (MEMS). The importance of MEMS devices lies in the fact that they
enable the realization of devices which are not possible to implement in a
larger scale. Nevertheless, integration of the whole system on the same
wafer or chips sounds inevitable because as device dimensions shrink the
sensitivity drops as the parasitics become more significant. Merging
electronics and mechanics in a single chip not only would improve the
sensitivity but also makes the power dissipation and chip area consumption
more efficient by eliminating the inter-chip interconnect parasitics.

The objective of this work is the feasibility of implementation of an
integrated three-dimensional ultrasonic imaging system using capacitor
macro-machined ultrasound trasducers (cMUTs). cMUTs as the leading edge
technology of choice for ultrasonic array transducers are fabricated using
CMOS compatible processes and prove to have a larger dynamic range and
percentage bandwidth compared to piezoelectric devices with fewer practical
limitations. In this research both fundamental and practical limitations for
the system are investigated and the techniques to allow the implementation
are developed. In order to construct an image, a novel beamforming
architecture has been proposed and the implementation of the whole system in
CMOS is investigated. Since medical ultrasound imaging constrains the
resolution of the signals to better than 10 bits, the implementation of
dedicated front-end electronics for reading the cMUT elements information
has been investigated and an analog to digital converter as the interface
for the digital beamforming processing has been designed and fabricated.
Pipelining along with multiplexing has been employed to make the design more
efficient and practical. The pipeline architecture offers area or speed
advantages over the flash or multistep approaches due to concurrent
processing of the analog signal. The experimental ADC prototype has been
implemented in 0.25um standard CMOS processes which achieves 10 bits of
resolution for 8 ultrasound channels of 10MHz bandwidth and occupies 2mmX2mm
of silicon area. The novel ADC architecture is expandable to address a
greater number of channels at the cost of more area and power.




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