(corrected) EE310 Integrated Circuits Seminar, 12/4/01

Ann Guerra guerra at par.stanford.edu
Thu Nov 29 15:58:06 PST 2001


EE310 Integrated Circuits Technology and Design Seminar


"A 5-GHz CMOS transceiver for IEEE 802.11a Wireless LAN"

		       David Su
		Atheros Communications

		Tuesday, December 4, 2001
			4:15 p.m.
		Building 380, Room 380X



		        ABSTRACT

High-speed wireless communications at 5-GHz, as specified by the
IEEE 802.11a Wireless LAN protocol, can provide data rates of up
to 54 Mbps.  This talk describes the design of the RF and analog
baseband functions of a Wireless LAN. The transceiver consists of
a transmitter, a receiver, a frequency synthesizer, biasing
circuitry, and control logic.   The transmitter, with an on-chip power
amplifier, has a maximum output power of 22 dBm. The receiver with
on-chip LNA and programmable baseband amplifiers, has an overall
noise figure of 8dB.  The frequency synthesizer has a phase noise
of -112dBc/Hz at 1MHz offset.   The transceiver is implemented in
a 0.25um CMOS technology with a die area of 22 sq mm.  It has also
been incorporated into a radio system to form a high-speed,
IEEE 802.11a-compliant wireless LAN.







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