From gray at ee.Stanford.EDU Mon Dec 2 10:34:25 2002 From: gray at ee.Stanford.EDU (Robert M. Gray) Date: Mon, 02 Dec 2002 10:34:25 -0800 Subject: Special Seminars (with Room Correction) Message-ID: <200212021834.gB2IYPE29635@ee.Stanford.EDU> Please note both talks are in the Packard EE Building Auditorium, Packard 101. Dr. Jelena Kovacevic of Bell Labs (Lucent) will be visiting Stanford December 3- December 5 and will be giving two special EE Seminars during her visit. The Wednesday talk is intended for a more general audience. Life After Wavelets: The War Of The Frames Jelena Kovacevic, Bell Labs Tuesday, December 3rd Noon Packard 101 ABSTRACT The addition of wavelets to the signal processing toolbox greatly enhanced our ability to deal with nonstationary signals. Its effects are felt beyond the research community through JPEG, now wavelet based. Frames -- redundant representations of which wavelets are a subclass -- are the next addition to the toolbox. Tight frames, in particular, with a few restrictions, become orthonormal bases. I talk here about finite tight frames, fundamental for a broad spectrum of applications. Until now it was thought that such frames were sparse. I show that actually tight frames are everywhere and they can be custom built for most applications as long as the requirements are not too rigid and do not violate the Fundamental Inequality which all tight frames must satisfy. This inequality governs the distribution of power among the frame vectors. In this ``war of the frames'', if the Fundamental Inequality is not satisfied, the dominant vectors grab dimensions to themselves and let the rest of the vectors squabble over the remaining dimensions. On the other hand, if the Fundamental Inequality holds, no vector is powerful enough to subjugate the rest, leading to equitable power sharing. Photo-to-Grandma Problem: Compression Meets the Network Jelena Kovacevic, Bell Labs Wednesday, December 4th 4:15p.m Packard 101 In communications, separating source coding from channel coding is a standard form of modularization. It makes things simple for us, and furthermore Shannon's Separation Principle allows us to feel that we are not going to suffer for it. For practical purposes, separation leads to big toolboxes of reusable tools. I'll examine certain communication scenarios and draw conclusion on the existing toolboxes. I'll show that there is life beyond multiresolution. In particular, in some communication scenarios, the information available at the source decoder is a subset of a small number of chunks of data. Then, the right tools for source coding are not the conventional ones, but rather multiple description codes. I'll conclude with demonstrations of multiple description speech and audio coders. --------------------------- Jelena Kovacevic received her PhD from Columbia University with Martin Vetterli in 1991 and has been at Bell Labs (now Lucent Technologies) since as well as an Adjunct Professor at Columbia. She is coauthor with Vetterli of "Wavelets and Subband Coding," Prentice Hall, Editor-in-Chief of the IEEE Transactions on Image Processing, and an IEEE Fellow. From jerabek at snf.stanford.edu Mon Dec 2 15:40:58 2002 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Mon, 2 Dec 2002 15:40:58 -0800 (PST) Subject: LRS-18 maskwriter Message-ID: To whom it may concern, Laser maskwriter is down with a serious problem. The stage laser interferometer reports X-interferometer signal low , movement inhibit or no stage air. Micronic field service has been called. I will keep you posted om a progress of repair. -Paul From gu at monano.com Mon Dec 2 15:51:18 2002 From: gu at monano.com (gu) Date: Mon, 02 Dec 2002 15:51:18 -0800 Subject: solid object printer Message-ID: <3DEBF1F6.4050201@monano.com> Hello all, Does anyone know a commercial solid-object printer which can print thermoplastic mold with resolution of 250 micro? Thank you. Gang Gu Molecular Nanosystems 977 Commercial Street Palo Alto, CA 94303 Tel 650-8454032 Fax 650-8462522 From kenney at SLAC.Stanford.EDU Tue Dec 3 12:55:17 2002 From: kenney at SLAC.Stanford.EDU (Chris Kenney) Date: Tue, 03 Dec 2002 12:55:17 -0800 (PST) Subject: Graphite and Silicon Carbide Materials Talk Message-ID: Thursday 2:00 PM, December 5, 2002 Stanford CISX Auditorium Graphite and Silicon Carbide Materials: Properties, Characteristics and Semiconductor Industry Applications Don Bray and Rex Sheppard POCO Specialty Materials Both graphite and silicon carbide are used in the semiconductor industry for critical chamber/process applications. This presentation will provide an overview of the properties and characteristics of graphite and silicon carbide materials. Physical, mechanical, electrical, thermal and chemical properties of the materials will be presented along with information on their manufacture. Semiconductor technology applications for graphite and silicon carbide will also be offered, focusing on Etch, Ion Implant, CVD Diffusion and Metallization process areas. POCO materials have been instrumental in the evolution of semiconductor-related technologies. POCO has been a manufacturer of quality graphites for over 35 years and a supplier to the semiconductor industry for more than 25 years. POCO further expanded material capability by acquiring the technology to convert graphite into silicon carbide and is the only manufacturer using this graphite- SiC conversion production method. Other POCO areas of expertise include the ability to enhance and modify materials through purification, impregnation, infiltration and coating. POCO's research & development facilities and material labs provide innovative material solutions to meet the demands of advancing technology. Speakers: Don Bray - Don Bray is General Manager, Technology and Development at POCO. In this role he is responsible for all research and product development activities, particularly new materials and applications. Mr. Bray received a co-masters in Ceramic Engineering and Metallurgy in 1981 from Iowa State University, Ames Iowa were he previously obtained a B.S in Ceramic Engineering. Prior to POCO he held various positions at Advanced Refractory Technologies (ART) in Buffalo, NY where his primary activities were focused on ceramic and metal composites and diamond coatings. He also worked at Alcoa Research Labs in Alcoa Center, PA. Mr. Bray has been a member of the American Ceramic Society since 1976 and was named a Fellow in 2000. In 1986 he was an Invited Speaker at the St. Louis Section meeting on Refactories and Chair of Engineering Ceramics Division in 1998. He is a Member, Presidents Industrial Advisory Council (PIAC) for the American Ceramic Society. Mr. Bray is also a member ASM, SAE, Sigma Xi, NICE, Keramos and a Past Member Board of Directors, Ceramic Association of New York. Mr. Bray has 8 patents, numerous publications and presentations, edited one book on Engineering Ceramics. Rex Sheppard - Rex Sheppard is Manager, Graphite Research & Development at POCO. In this role he is responsible for all research and development activities relate to Graphite. Dr. Sheppard received his Ph.D. in Organic Chemistry in 1980 from North Texas State University, Denton, Texas and a B.S. in Chemistry in 1972 from Southwestern State College, Weatherford, Oklahoma. In addition he holds a MBA from the University of North Texas, Denton Texas. Dr. Sheppard joined POCO in 1983. Previously he was a Development Chemist from 1980 - 1982 at Celanese Chemicals Corporation. >From 1972 - 1974 he taught High School chemistry, Physics & Mathematics and assisted in Development of Nations Playoff System for High School Athletics Mombasa Baptist High School, Mombasa, Kenya, East Africa. He is a member of the American Chemical Society for 28 years (1974), Alpha Chi Sigma for 27 years (1975) and the American Carbon Society for 16 years (1985). From mwolfson at exajoule.com Wed Dec 4 12:45:42 2002 From: mwolfson at exajoule.com (Michael Wolfson) Date: Wed, 4 Dec 2002 12:45:42 -0800 Subject: Nikon LSA help Message-ID: <200212042045.MAA04876@pine.he.net> Hi, I'm having some trouble figuring out how to tell the Nikon where to find my LSA marks. I'd really appreciate if some experienced user could help me generate a working configuration file. Thanks, -- Michael Wolfson From jerabek at snf.stanford.edu Thu Dec 5 08:45:56 2002 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Thu, 5 Dec 2002 08:45:56 -0800 (PST) Subject: lrs-18 mask writer Message-ID: It looks like mask writer has been fixed. Yesterday I have ran 8 masks without an error so I keep my fingers crossed, hoping the problem was finaly fixed. However right now I have 30 mask backlog and will try to work it down as fast as I can. -Paul From jerabek at snf.stanford.edu Thu Dec 5 13:28:05 2002 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Thu, 5 Dec 2002 13:28:05 -0800 (PST) Subject: LRS-18 mask writer Message-ID: I have spoken too soon.System is down again, but this time with entirely different problem. It won't stay in focus. Normaly once properly calibrated the system should stay in focus for months. It was calibrated yesterday, but now just after about 24 hrs.it's out of focus.I have colled Micronic field engineering to address the problem. -Paul From jules83 at stanford.edu Fri Dec 6 15:18:11 2002 From: jules83 at stanford.edu (Julia R Greer) Date: Fri, 6 Dec 2002 15:18:11 -0800 Subject: Does anyone know how to strip Gold? Message-ID: <012201c29d7d$bf18c6a0$d37640ab@Touffler> Hey-ya, nanofabrication experts, It's me, the gold nanopillar person bugging you again. I am sorry, but I was wondering if anyone knew of a simple way (like the wet bench of some sort) to strip Gold and Titanium off of the nitride on the wafer. I have a film of Gold on top of the wafer surface that should have gone on the Titanium first, and I am wondering if I can re-use the wafer. Thank you! -Julia If you do not have 83,000 problems to worry about, it is not a stressful day! -------------- next part -------------- An HTML attachment was scrubbed... URL: From jerabek at snf.stanford.edu Tue Dec 10 09:22:04 2002 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Tue, 10 Dec 2002 09:22:04 -0800 (PST) Subject: LRS-18 mask writer Message-ID: Laser mask writer has been running for past three days without a problem. -Paul From jerabek at snf.stanford.edu Tue Dec 10 15:00:42 2002 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Tue, 10 Dec 2002 15:00:42 -0800 (PST) Subject: LSR-18 mask writer Message-ID: It looks like I have spoken too soon. Writer is down once again with a problem of spurious exposures.It seems to me the blanker is not working properly.Called Micronic to address the issue. -Paul From mtang at snf.stanford.edu Wed Dec 11 14:20:31 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 11 Dec 2002 14:20:31 -0800 Subject: Reminder: Lab Cleanup! Message-ID: <3DF7BA2F.BD089D88@snf.stanford.edu> Greetings Labmembers! Just a reminder that in conjunction with the holiday lab shutdown, there is a lab cleanup! 1. Bunnysuits: Please help us by putting your bunnysuit into the laundry bin when you are done for the year. You can really help by removing any personal items (badges, glasses, pens) from your bunnysuit. 2. Items in the lab: Unless they are stored inside personal bins, all personal items must be removed from the lab (this means test wafers, wafer boxes, and portable tool boxes!) -- by Monday, December 16. If you have personal items that you will need to work in the lab during the week of the 16th, they should be marked by red dots (available in the gowning room) so that we know this is work-in-progress. During shutdown, however, all personal items, red-dotted or not, will be removed from the lab. (Sorry folks, but there's an invasion of unlabeled boxes and other materials, so extreme measures have become necessary...) Thanks for your attention -- Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From maxy at stanford.edu Thu Dec 12 10:40:25 2002 From: maxy at stanford.edu (Dae-han Choi) Date: Thu, 12 Dec 2002 10:40:25 -0800 Subject: SOI wafer vendor References: <3DF7BA2F.BD089D88@snf.stanford.edu> Message-ID: <003101c2a20d$efd69fd0$617640ab@max> Dear members, Hello, I'm trying to buy 4~5 SOI wafers with the following specs. But some vendors have a minimum number of wafers to order, such as 10. Does anyone know a good vendor I can contact? Specs of SOI wafers I'm looking for are ..... Diameter: 4" Device layer: 80 microns Thermal Oxide: 1~1.5 microns Si under Thermal Oxide: 500 microns orientation: <100> Dopant: either N or P type, resistivity ~10 ohm-cm Thank you in advance for any advice. Dae-han ===================================== Dae-han Choi Ph.D. Candidate Materials Science and Engineering Stanford University Phone : +1-650-736-2141 From Spotworthy at aol.com Thu Dec 12 11:05:51 2002 From: Spotworthy at aol.com (Spotworthy at aol.com) Date: Thu, 12 Dec 2002 14:05:51 -0500 Subject: SOI wafer vendor Message-ID: <6F03B49F.5AAC9ED4.0CEC25E7@aol.com> You might try Analoge Devices Inc. They bought BCO of Ireland a couple of years ago. This is where I got my SOI wafers a year ago. I'm not sure if they have a mininum quantity requirement though. You could try Polishing Corp of America. They are located in Santa Clara, down by the airport. They are a wafer broker, and they may be able to find you what you are looking for. You also might ask Tony souza where he gets his wafers. From rdasher at cis.Stanford.EDU Thu Dec 12 11:13:51 2002 From: rdasher at cis.Stanford.EDU (Richard Dasher) Date: Thu, 12 Dec 2002 11:13:51 -0800 (PST) Subject: Lunch with Infineon Technologies tomorrow Message-ID: Hi Everyone, CIS is hosting a visit on Friday, 12/13 by Dr. Georg Schulze-Icking and Dr. Harald Seidl of Infineon Technologies, Munich. We'd like to invite you to come to their informal lunch-presentation about Infineon's work and interests in device and process modeling, high-k dielectric materials, and related topics. This is in the Linvill Room, CIS 101, from 12:15 pm. We've ordered Chinese food. Please let Maureen Rochford know if you think you can come (maureen at cis, 5-3627). Richard ------------------------------------------------- Richard B. Dasher, Ph.D. TEL 1-650-725-3621 Stanford University Executive Director, Center for Integrated Systems FAX 1-650-725-0991 http://cis.stanford.edu Director, US-Asia Technology Management Center FAX 1-650-725-9974 http://asia.stanford.edu ------------------------------------------------- From jun.f.zheng at intel.com Thu Dec 12 11:25:36 2002 From: jun.f.zheng at intel.com (Zheng, Jun F) Date: Thu, 12 Dec 2002 11:25:36 -0800 Subject: SOI wafer vendor Message-ID: <621F928C3A39D61185C700508BB268435E8343@fmsmsx101.fm.intel.com> Try the following: Susan Fredrick Sales Administrator SOITEC/USA phone (978)531-1415 fax (978)531-2758 -----Original Message----- From: Dae-han Choi [mailto:maxy at stanford.edu] Sent: Thursday, December 12, 2002 10:40 AM To: labmembers at snf.stanford.edu Subject: SOI wafer vendor Dear members, Hello, I'm trying to buy 4~5 SOI wafers with the following specs. But some vendors have a minimum number of wafers to order, such as 10. Does anyone know a good vendor I can contact? Specs of SOI wafers I'm looking for are ..... Diameter: 4" Device layer: 80 microns Thermal Oxide: 1~1.5 microns Si under Thermal Oxide: 500 microns orientation: <100> Dopant: either N or P type, resistivity ~10 ohm-cm Thank you in advance for any advice. Dae-han ===================================== Dae-han Choi Ph.D. Candidate Materials Science and Engineering Stanford University Phone : +1-650-736-2141 From dwshin at Stanford.EDU Thu Dec 12 11:52:45 2002 From: dwshin at Stanford.EDU (Dong-Woon Shin) Date: Thu, 12 Dec 2002 11:52:45 -0800 (PST) Subject: SOI wafer vendor In-Reply-To: <003101c2a20d$efd69fd0$617640ab@max> Message-ID: Hi, Daehan There is a customized wafer vendor named " Universitywafers.com" If the address is not correct, try to find it in google or yahoo. Thanks. This e-mail was carboncopied just FYI for other users at SNF. On Thu, 12 Dec 2002, Dae-han Choi wrote: > Dear members, > > Hello, > I'm trying to buy 4~5 SOI wafers with the following specs. > But some vendors have a minimum number of wafers to order, such as 10. > Does anyone know a good vendor I can contact? > > Specs of SOI wafers I'm looking for are ..... > > Diameter: 4" > Device layer: 80 microns > Thermal Oxide: 1~1.5 microns > Si under Thermal Oxide: 500 microns > orientation: <100> > Dopant: either N or P type, resistivity ~10 ohm-cm > > > Thank you in advance for any advice. > > Dae-han > > ===================================== > > Dae-han Choi > Ph.D. Candidate > Materials Science and Engineering > Stanford University > Phone : +1-650-736-2141 > From cshen at briontech.com Wed Dec 18 15:15:34 2002 From: cshen at briontech.com (cshen at briontech.com) Date: Wed, 18 Dec 2002 15:15:34 -0800 (PST) Subject: Dry etch oxide In-Reply-To: <63640.171.64.100.112.1040253235.squirrel@mail.briontech.com> References: <63640.171.64.100.112.1040253235.squirrel@mail.briontech.com> Message-ID: <63674.171.64.100.112.1040253334.squirrel@mail.briontech.com> Dear labmembers, Does anybody know how to etch SiOx in Drytek1? I tryied CF4 and SF6, neither worked. The SiOx was deposited using sputtering.Thank you for your help. Chongfei From mahnaz at snf.stanford.edu Thu Dec 19 11:03:10 2002 From: mahnaz at snf.stanford.edu (Mahnaz) Date: Thu, 19 Dec 2002 11:03:10 -0800 Subject: Kind reminder Message-ID: <3E0217EE.7962122F@snf.stanford.edu> Hello all, Please discard your lab garments by tonight ( Thursday 12/19) as we have arranged for extra garment pick up tomorrow 12/20. We will bring the rest of the garment down to be send out for clean. Please collect and put your stuff in your bins, particularly stuff on the WIP rack needs to be collected as there will be a lot of activity and I will not be responsible for the damages to those boxes and masks left on the rack. If you need assistance let me know. mahnaz From vincent at missionctrl.com Sun Dec 15 16:44:23 2002 From: vincent at missionctrl.com (Vincent Bressler) Date: Sun, 15 Dec 2002 16:44:23 -0800 Subject: Dicing thick glass wafer Message-ID: <3DFD21E7.3010204@missionctrl.com> I have a 0.75 mm thick 100mm diameter glass wafer. I need to dice it with cut lines no more than 1mm wide. Does anyone have any suggestions?