Special ISSCC Presentation, Tues 1/15
guerra at par.stanford.edu
Tue Jan 8 20:55:00 PST 2002
will give his ISSCC presentation:
"A 3V SD Receiver with Sampling Rate Enhancement
for CDMA Baseband-Processor IC"
Tuesday, January 15, 2002
A 3V SD CDMA baseband receiver has a 4th-order single-loop modulator that
enhances the effective sampling rate without increasing the actual rate,
achieves 62dB DR, consumes 22mW, and occupies 1.3mm2 in 0.25um CMOS. The
8M transistor 10.5x10.5mm2 chip integrates receiver, transmitter, voice
codec, 10b ADC and DAC, PLL, 32kHz oscillator, two DSP, memory, and ARM.
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