Special ISSCC Presentation, Tues 1/29 - Time Interleaving Background Calibration

[Ann Guerra]

		     Shafiq M. Jamal
		  Marvell Semiconductor
	     will give his ISSCC presentation:

 "A 10b 120MSample/s Time-Interleaved Analog-to-Digital
  Converter withDigital Background Calibration" (10.4)

		Tuesday, January 29, 2002
			3:30 p.m.
			 CIS-101


		 	 ABSTRACT

Digital calibration using adaptive signal processing corrects offset
mismatch, gain mismatch, and sample-time error between time-interleaved
channels in a 10b 120MSample/s pipelined ADC.  With background
calibration, peak SNDR is 56.8dB and power dissipation is 234mW from 3.3V.
Active area is 12.5mm2 in 0.35um CMOS.