Philips Thurs 1/31 - ISSCC presentations

Ann Guerra guerra at
Thu Jan 24 13:58:53 PST 2002

This year's visit by Philips Research on their way to ISSCC will be on
Thursday, January 31.  Members of the Mixed-Signal Circuits and Systems
group will give three ISSCC presentations, to be followed by discussions

	    Thursday, January 31, 2002
		    10:00 a.m.

1.		Peter Scholtens

"A 6b 1.6GSample/s Flash ADC in 0.18um CMOS Using
	Averaging Termination" (10.2)

A 1.6GSample/s 6b flash analog-to-digital converter in 0.18um CMOS for
storage read channels is described.  The array of amplifiers and averaging
resistors is terminated with less overrange while maintaining full-scale
linearity.  Consuming 340mW, it achieves 5.7 effective bits at DC and 5
effective bits at 660 MHz.

2.	   Robert van Veldhoven

"A 3.3mW Sigma-Delta Modulator for UMTS in 0.18um
CMOS with 70dB Dynamic Range in 2MHz Bandwidth" (13.5)

A 4th-order, continuous-time sigma-delta modulator with 1.5b quantizer and
feedback DAC for a UMTS receiver has 70dB DNR in a 2MHz band and -74dB THD
at full scale.  An IC including two modulators, a PLL and an oscillator
dissipates 11.5mW at 1.8V.  Active area is 0.41mm2 in 0.18um, 1 poly and
5-metal-layer CMOS technology.

3.	      Stefan Menten

   "A 10uV-Offset 8kHz-Bandwidth 4th-Order Chopped
Sigma-Delta A/D Converter for Battery Management" (23.5)

A chopped 5th-order continuous-time 1b sigma-delta A/D converter with 10uV
offset and 8kHz bandwidth is for battery current measurement.  Chopping at
16kHz, the circuit has a 0.1V input range, a 68dB SNR, and a 1MHz output
bit rate.  Area is 0.45x0.4mm2 in 0.35um CMOS.  Current consumption is
30uA at 2.5-4V.

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