ISSCC practice talk by Jaeha Kim

Jaeha Kim jaeha at
Mon Jan 28 11:19:24 PST 2002

Dear colleagues and faculties:

I am giving a practice talk for ISSCC on Thursday 3-4pm at CIS 101. I
would be very grateful if you can come by and help me improve my talk.

"Adaptive Supply Serial Links with Sub-1V Operation and Per-pin Clock
Recovery (#16.3)"

January 31, Thursday, 3:00pm-4:00pm, CIS 101

Low power consumption of high-speed links has become a critical factor as
the applications demand more links integrated on a single chip. Previous
work demonstrated that adaptive power-supply regulation can significantly
improve the energy efficiency of parallel links and that it can scale
various link properties with the bitrate by exploiting the adaptive supply
as the global bias.

This work extends the adaptive supply to serial links. Higher parallelism
in each transmitter and receiver improves both speed and power of a link
when it operates at the adaptive supply. Various low-voltage circuit
techniques are presented to extend the lower supply limit of the link down
to 1.6*Vth. Dual-loop per-pin clock recovery PLL that uses the adaptive
power-supply regulator as the coarse-tuning loop is also presented. The
adaptive supply serial link operates at 0.45-3.7Gb/s for 0.9-2.5V supply
and dissipates 9.2-197mW.

Thank you very much,

  Jaeha Kim                             jaeha at
  CIS 065                               P.O. Box 16311 
  Stanford University                   Stanford, CA 94309
  (650)725-3730                         (650)960-2419                         

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