From mtang at snf.stanford.edu  Fri Nov  1 13:20:23 2002
From: mtang at snf.stanford.edu (Mary Tang)
Date: Fri, 01 Nov 2002 13:20:23 -0800
Subject: Surveys!!!
Message-ID: <3DC2F017.51A910D1@snf.stanford.edu>

Okay, okay --  One very LAST chance to get your labmember surveys in and
win  prize!!!  We're taking surveys until Monday, 11/4.  Blank survey
forms are available outside the gowning room and on the web at:
http://snf.stanford.edu/Labmembers/Survey.html

Please, please help us in our NSF reporting by turning your survey in!

Mary

--
Mary X. Tang, Ph.D.
National Nanofabrication Users' Network
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at snf.stanford.edu




From mtang at snf.stanford.edu  Fri Nov  1 17:07:56 2002
From: mtang at snf.stanford.edu (Mary Tang)
Date: Fri, 01 Nov 2002 17:07:56 -0800
Subject: Personal files on CAD PC's
Message-ID: <3DC3256C.7807021D@snf.stanford.edu>

Hello Labmembers --

First, the LEdit PC in the CAD room has now been repaired (thanks to
Mike Bell!)  Second, as you are probably well aware, the CAD PC's are a
bit on the mature side and don't have scads of disk space...  Please,
please, please backup your files and delete any that you don't need to
have on a shared system.  And please do not add any programs to these
PC's, at least not without checking with SNF staff members first.

I'm sorry to have to implement harsh measures but...  starting December
2, personal files older than 6 months may be subject to removal.  And
programs (like the "Matrix Reloaded" trailer) not deemed essential to
lab activities may also be removed.

Thanks for your attention --

Mary

--
Mary X. Tang, Ph.D.
National Nanofabrication Users' Network
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at snf.stanford.edu




From curlwang at stanford.edu  Fri Nov  1 17:59:58 2002
From: curlwang at stanford.edu (Ke Wang)
Date: Fri, 1 Nov 2002 17:59:58 -0800 (PST)
Subject: cheap masks 
Message-ID: <Pine.GSO.4.44.0211011749360.18554-100000@elaine30.Stanford.EDU>

Hello,

I wish to make a lot of masks with non-critical feature size
(~40um). I remember there is kind of "transparency" mask that is really cheap.
Does anybody know that if I'll have to go to a vendor (as on snf website),
or I can just print them out by myself?

Thanks a lot! And nice weekend!

Ke







From eadensaw at hotmail.com  Sat Nov  2 22:55:50 2002
From: eadensaw at hotmail.com (Eaden Saw)
Date: Sat, 2 Nov 2002 22:55:50 -0800
Subject: cheap masks
References: <Pine.GSO.4.44.0211011749360.18554-100000@elaine30.Stanford.EDU>
Message-ID: <OE34207TlH3Nl25D3Na0000aae5@hotmail.com>

HI Ke,

I believe that you can print the transparencies yourself with a printer of
640 dpi or higher.  Since 640 dpi has resolution better than 40 micron.

The web page at SNF: //snf.stanford.edu/Process/Masks/mylar.html suggests
that by using a 3600 or better, photoreproduction quality laser printer, you
can generate a transparency with geometries defined down to the tens of
microns in resolution.

I am not sure how can a 3600 dpi printer produce sub micron resolution.  By
calculation, 3600 dpi should only be able to resolve 7 micron line.

Eaden
----- Original Message -----
From: "Ke Wang" <curlwang at stanford.edu>
To: <labmembers at snf.Stanford.EDU>
Sent: Friday, November 01, 2002 5:59 PM
Subject: cheap masks


> Hello,
>
> I wish to make a lot of masks with non-critical feature size
> (~40um). I remember there is kind of "transparency" mask that is really
cheap.
> Does anybody know that if I'll have to go to a vendor (as on snf website),
> or I can just print them out by myself?
>
> Thanks a lot! And nice weekend!
>
> Ke
>


From katsuo at umich.edu  Mon Nov  4 12:49:47 2002
From: katsuo at umich.edu (Katsuo Kurabayashi)
Date: Mon, 04 Nov 2002 15:49:47 -0500
Subject: Gold Electroplating
Message-ID: <5.1.0.14.2.20021104152928.03f7fc28@srvr5.engin.umich.edu>

Hello SNF lab users,

My group at University of Michigan wants to deposit a 2-3 micron thick Au 
film using electroplating. Is there anybody who uses Au electroplating at 
SNF? If there is, I would like to contact that person.

Thank you,

*************************************************************
Katsuo Kurabayashi, Ph.D.
Assistant Professor
Mechanical Engineering &
Macromolecular Science and Engineering
University of Michigan

Room 2272 G.G. Brown Lab
Ann Arbor, MI 48109-2125

Tel:    (734) 615-5211
Fax:    (734) 647-3170
e-mail: katsuo at umich.edu
Web: http://www-personal.umich.edu/~katsuo
***************************************************************



From mtang at snf.stanford.edu  Mon Nov  4 14:07:13 2002
From: mtang at snf.stanford.edu (Mary Tang)
Date: Mon, 04 Nov 2002 14:07:13 -0800
Subject: Gold Electroplating
References: <5.1.0.14.2.20021104152928.03f7fc28@srvr5.engin.umich.edu>
Message-ID: <3DC6EF91.4D3997C6@snf.stanford.edu>

Hello Katsuo (and Labmembers):

We currently do not support electroplating at SNF (although if anyone is
interested, we'd be interested in discussing this.)  There are some resources
just listed on the website
(http://snf.stanford.edu/Process/Resources/Electroplating.html) although it's
been quite some time since these have been confirmed by other labmembers...
(Does anyone have any favorite sources or contacts to add?)

Mary

Katsuo Kurabayashi wrote:

> Hello SNF lab users,
>
> My group at University of Michigan wants to deposit a 2-3 micron thick Au
> film using electroplating. Is there anybody who uses Au electroplating at
> SNF? If there is, I would like to contact that person.
>
> Thank you,
>
> *************************************************************
> Katsuo Kurabayashi, Ph.D.
> Assistant Professor
> Mechanical Engineering &
> Macromolecular Science and Engineering
> University of Michigan
>
> Room 2272 G.G. Brown Lab
> Ann Arbor, MI 48109-2125
>
> Tel:    (734) 615-5211
> Fax:    (734) 647-3170
> e-mail: katsuo at umich.edu
> Web: http://www-personal.umich.edu/~katsuo
> ***************************************************************

--
Mary X. Tang, Ph.D.
National Nanofabrication Users' Network
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at snf.stanford.edu





From Farhat_Quli at SensArray.com  Mon Nov  4 14:27:59 2002
From: Farhat_Quli at SensArray.com (Farhat Quli)
Date: Mon, 4 Nov 2002 14:27:59 -0800 
Subject: Gold Electroplating
Message-ID: <6B29DC48E741BE46B96884DEC25BE66608A189@uhura.sensarray.com>

I have had good results with gold, nickel, and palladium
films plated at Peninsula Coating Services in Santa Clara
(on PC boards and cables, not wafers).

Contact the owner, Jack Underwood (408) 748-1420


-Farhat



From tsung-kuan.allen.chou at intel.com  Mon Nov  4 16:31:09 2002
From: tsung-kuan.allen.chou at intel.com (Chou, Tsung-Kuan Allen)
Date: Mon, 4 Nov 2002 16:31:09 -0800 
Subject: Gold Electroplating
Message-ID: <ADCE7AEB26CBD511B4D100508B66D3060387F174@fmsmsx115.fm.intel.com>

Katsuo,

FYI in case you didn't know. The SSEL at U of Michigan does have Au plating
hood in GaAs bay. I was there until last year.

Regards,

Allen

-----Original Message-----
From: Katsuo Kurabayashi [mailto:katsuo at umich.edu]
Sent: Monday, November 04, 2002 12:50 PM
To: labmembers at snf.stanford.edu
Subject: Gold Electroplating


Hello SNF lab users,

My group at University of Michigan wants to deposit a 2-3 micron thick Au 
film using electroplating. Is there anybody who uses Au electroplating at 
SNF? If there is, I would like to contact that person.

Thank you,

*************************************************************
Katsuo Kurabayashi, Ph.D.
Assistant Professor
Mechanical Engineering &
Macromolecular Science and Engineering
University of Michigan

Room 2272 G.G. Brown Lab
Ann Arbor, MI 48109-2125

Tel:    (734) 615-5211
Fax:    (734) 647-3170
e-mail: katsuo at umich.edu
Web: http://www-personal.umich.edu/~katsuo
***************************************************************


From jqguo at stanford.edu  Tue Nov  5 10:36:29 2002
From: jqguo at stanford.edu (Jiquan Guo)
Date: Tue, 5 Nov 2002 10:36:29 -0800 (PST)
Subject: ion implantation vendors in Palo Alto?
Message-ID: <Pine.GSO.4.44.0211051029190.19288-100000@elaine23.Stanford.EDU>

Hello, labmembers,

I'm looking for some vendors doing ion implant. I've found some in Santa
Clara or San Jose on snf website. But I heard that there are some just in
Palo Alto. Does anyone know the contact of those vendors?

Jiquan Guo

SLAC, MS 26
2575 SandHill Road
Menlo Park, CA 94025

Phone:      (650)926 2898(O)



From grupp at snowmass.Stanford.EDU  Tue Nov  5 11:12:45 2002
From: grupp at snowmass.Stanford.EDU (Dan Grupp)
Date: Tue, 5 Nov 2002 11:12:45 -0800 (PST)
Subject: ion implantation vendors in Palo Alto?
In-Reply-To: <Pine.GSO.4.44.0211051029190.19288-100000@elaine23.Stanford.EDU>
Message-ID: <Pine.GSO.4.43.0211051110020.16126-100000@snowmass>

cheapest and most reliable i have found:
Nu Ions 408-437-5761. They are near SJ airport, but I just use ASAP
delivery to send them there and back (about $60 round-trip, gets there in
two hours - let them sit in traffic!), 347-2727.
Good luck,
dan

ps - if you gather more info, please have it put onto snf Web site!

On Tue, 5 Nov 2002, Jiquan Guo wrote:

> Hello, labmembers,
>
> I'm looking for some vendors doing ion implant. I've found some in Santa
> Clara or San Jose on snf website. But I heard that there are some just in
> Palo Alto. Does anyone know the contact of those vendors?
>
> Jiquan Guo
>
> SLAC, MS 26
> 2575 SandHill Road
> Menlo Park, CA 94025
>
> Phone:      (650)926 2898(O)
>
>

---------------------------------------------------------------------------
Dr. Daniel Grupp, Visiting Scholar
Center for Integrated Systems
Stanford University
Stanford, CA 94305
(650) 724-6911
FAX:  723-4659
---------------------------------------------------------------------------



From jules83 at stanford.edu  Wed Nov  6 12:11:25 2002
From: jules83 at stanford.edu (Julia R Greer)
Date: Wed, 6 Nov 2002 12:11:25 -0800
Subject: Gold nanopillars and such
Message-ID: <024801c285d0$b2018110$d37640ab@Touffler>

Hello fellow CIS users,

I was wondering if anyone had experience with depositing 3um Gold on Si
wafers. I was recommended making "short stubs" by the Lift-Off process
(~2500A tall) and then electroplating them up to the 3um thickness. Does
anyone have any experience with doing similar things? Any inputs would
be MUCH appreciated especially if you have some good electroplating
vendors in mind!

Thank you!
--Julia

If you do not have 83,000 problems to worry about, it is not a stressful
day!


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From kcrozier at leland.stanford.edu  Wed Nov  6 14:49:46 2002
From: kcrozier at leland.stanford.edu (Kenneth Brian Crozier)
Date: Wed, 06 Nov 2002 14:49:46 -0800
Subject: PhD Oral Defense - Ken Crozier
Message-ID: <3.0.3.32.20021106144946.00f3872c@kcrozier.pobox.stanford.edu>

PhD Oral Defense Seminar, Department of Electrical Engineering

Micromachined Solid Immersion Lenses and Optical Antennas for 
Scanning Nearfield Optical Microscopy

Kenneth Crozier

Advisors : Professors C.F. Quate and G.S. Kino

Wednesday, November 13, 9am
Center for Integrated Systems (Extension) Auditorium, CIS-X
Refreshments at 8:45am

ABSTRACT

  The optical microscope is a powerful and ubiquitous measurement and
observation tool in science, medicine and industry.  In spite of this,
however, the resolving power of the optical microscope is fundamentally
limited by diffraction.  Two points on a sample may only be resolved if
they are separated by more than ~ 0.61*lambda (Rayleigh criterion), where
lambda is the optical wavelength in air.  In this work we demonstrate two
methods to overcome this limitation based on micromachined Solid Immersion
Lenses (SILs) and optical antennas.

  In the first method for improving optical resolution, the Solid Immersion
Lens (SIL), light is focussed in a high refractive index lens held close to
the sample.  Silicon nitride SILs with diameters of ~7 micron integrated
with atomic force microscope cantilevers are fabricated by surface
micromachining.  A scanning optical microscope based on the micromachined
SILs and operating in reflection and transmission modes at a wavelength of
400nm is presented.  The full width at half maximum spot size of the
SIL-based microscope is measured to be ~130nm, which is ~1.9 times better
than the spot size without the SIL (256nm).  Furthermore, the optical
transmission efficiency of the SIL is ~64% (with losses due to reflection
and absorption), which is significantly better than that of the tapered
fiber nearfield scanning optical microscope (typically ~0.001-0.01%).

  The second method for improving resolution uses antennas operating at
optical wavelengths to enhance the optical fields in regions whose
dimensions are much smaller than the wavelength.  We present a numerical
study based on the finite difference time domain (FDTD) technique, showing
that the optical intensity is enhanced by three orders of magnitude in a
region whose dimensions are less than ~lambda/40.  A study on the factors
influencing intensity enhancement is presented.  Optical antennas operating
at infrared wavelengths (~2-10 micron) are fabricated by electron-beam
lithography.  Far-field measurements on the optical antennas are carried
out and found to be in good agreement with FDTD calculations.




From yy7343 at hotmail.com  Wed Nov  6 16:38:03 2002
From: yy7343 at hotmail.com (Yahong Yao)
Date: Wed, 06 Nov 2002 16:38:03 -0800
Subject: chip curvature measurement?
Message-ID: <F15Bu5aTRsZSscM8tsx00012e39@hotmail.com>

Dear Users,

I am looking for a way to measure the curvature of a MEMS chip (size: 
3mm*3mm*0.5mm).

When we deposit films on one side of the Si wafer, due to the residue stress 
of the films the wafer bends.  It is easy to measure the curvature of the 
wafer by laser beam scanning.  If we dice the wafer into pieces (chips) as 
above size, how could we measure the curvature of the chips?  I think it 
might not be accurate to calculate the chip curvature according to the wafer 
curvature since the center of the chip is etched out, in another words, the 
remaining bulk Si part is just a frame (about 1/3 of the volume in center is 
etched away).

Does any one know what tool and which company does this job?  Thanks in 
advance.

Yahong



_________________________________________________________________
The new MSN 8: advanced junk mail protection and 2 months FREE* 
http://join.msn.com/?page=features/junkmail



From afflannery at attbi.com  Wed Nov  6 17:08:42 2002
From: afflannery at attbi.com (Anthony Flannery)
Date: Wed, 6 Nov 2002 17:08:42 -0800
Subject: chip curvature measurement?
References: <F15Bu5aTRsZSscM8tsx00012e39@hotmail.com>
Message-ID: <000701c285fa$38bdb470$8501a8c0@transparentnetworks.com>

The SMSI stress guage can be programmed to scan just chips. Be careful not
to mess up the default settings if you go in there to program it.

Tony Flannery

----- Original Message -----
From: "Yahong Yao" <yy7343 at hotmail.com>
To: <labmembers at snf.stanford.edu>
Sent: Wednesday, November 06, 2002 4:38 PM
Subject: chip curvature measurement?


> Dear Users,
>
> I am looking for a way to measure the curvature of a MEMS chip (size:
> 3mm*3mm*0.5mm).
>
> When we deposit films on one side of the Si wafer, due to the residue
stress
> of the films the wafer bends.  It is easy to measure the curvature of the
> wafer by laser beam scanning.  If we dice the wafer into pieces (chips) as
> above size, how could we measure the curvature of the chips?  I think it
> might not be accurate to calculate the chip curvature according to the
wafer
> curvature since the center of the chip is etched out, in another words,
the
> remaining bulk Si part is just a frame (about 1/3 of the volume in center
is
> etched away).
>
> Does any one know what tool and which company does this job?  Thanks in
> advance.
>
> Yahong
>
>
>
> _________________________________________________________________
> The new MSN 8: advanced junk mail protection and 2 months FREE*
> http://join.msn.com/?page=features/junkmail
>



From shott at snf.stanford.edu  Thu Nov  7 07:57:31 2002
From: shott at snf.stanford.edu (John Shott)
Date: Thu, 07 Nov 2002 07:57:31 -0800
Subject: Enable/disable equipment problems last night ...
Message-ID: <3DCA8D6B.AE928161@snf.stanford.edu>

SNF lab members:

Last night, several of you noticed problems enabling and disabling equipment. 
Ironically, this turned out to be due to a failure of the uninterruptible
power supply attached to the hardware interlock computer.  As soon as power
was returned, all of those enable/disable requests (that had, in effect, been
pending overnight ...) went through.  If you were working last night, please
check the current enable/disable status to make sure that it ended up in the
proper state.  If you notice any problems, please contact me.

We apologize for this inconvenience ... the UPS is supposed to make our
operation more reliable, not less!

Thank you for your continued support,

John


From omar at siliconlight.com  Wed Nov  6 18:28:59 2002
From: omar at siliconlight.com (Omar Leung)
Date: Wed, 6 Nov 2002 18:28:59 -0800 
Subject: chip curvature measurement?
Message-ID: <8B91B41B86B7D4118E390003470A02E3DC1B20@crum.internal.siliconlight.com>

Sounds like you have a film membrane in a silicon frame?

1st are you sure the membrane will survive the dice?
2nd you are right, your chip will not have the same curvature as a unetched
wafer.

I would think the best way to measure such a structure in the lab would be
to expand and collimate a laser beam, then measure the focal length.
Alternately, you could put the laser on a micrometer stage and move it
across your sample while you measure the position of the beam.

This is essentially how the SMSI and Flexus machines work anyway.

If you want more accurate results use a white light interferometer
(Veeco/WYKO).

Omar

-----Original Message-----
From: Yahong Yao [mailto:yy7343 at hotmail.com]
Sent: Wednesday, November 06, 2002 4:38 PM
To: labmembers at snf.stanford.edu
Subject: chip curvature measurement?


Dear Users,

I am looking for a way to measure the curvature of a MEMS chip (size: 
3mm*3mm*0.5mm).

When we deposit films on one side of the Si wafer, due to the residue stress

of the films the wafer bends.  It is easy to measure the curvature of the 
wafer by laser beam scanning.  If we dice the wafer into pieces (chips) as 
above size, how could we measure the curvature of the chips?  I think it 
might not be accurate to calculate the chip curvature according to the wafer

curvature since the center of the chip is etched out, in another words, the 
remaining bulk Si part is just a frame (about 1/3 of the volume in center is

etched away).

Does any one know what tool and which company does this job?  Thanks in 
advance.

Yahong



_________________________________________________________________
The new MSN 8: advanced junk mail protection and 2 months FREE* 
http://join.msn.com/?page=features/junkmail



__________________________________________________
The WebShield e500 Appliance has scanned
this email message and attachments for viruses.


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From intelbalaji at yahoo.com  Wed Nov  6 18:30:50 2002
From: intelbalaji at yahoo.com (Balaji Venkateshwaran)
Date: Wed, 6 Nov 2002 18:30:50 -0800 (PST)
Subject: chip curvature measurement?
In-Reply-To: <F15Bu5aTRsZSscM8tsx00012e39@hotmail.com>
Message-ID: <20021107023050.98407.qmail@web12802.mail.yahoo.com>

Yahong,

Not sure if this suits your need, but I think Zygo
offers sample curvature measurement services (using
laser interferometry).
www.zygo.com

Balaji


--- Yahong Yao <yy7343 at hotmail.com> wrote:
> Dear Users,
> 
> I am looking for a way to measure the curvature of a
> MEMS chip (size: 
> 3mm*3mm*0.5mm).
> 
> When we deposit films on one side of the Si wafer,
> due to the residue stress 
> of the films the wafer bends.  It is easy to measure
> the curvature of the 
> wafer by laser beam scanning.  If we dice the wafer
> into pieces (chips) as 
> above size, how could we measure the curvature of
> the chips?  I think it 
> might not be accurate to calculate the chip
> curvature according to the wafer 
> curvature since the center of the chip is etched
> out, in another words, the 
> remaining bulk Si part is just a frame (about 1/3 of
> the volume in center is 
> etched away).
> 
> Does any one know what tool and which company does
> this job?  Thanks in 
> advance.
> 
> Yahong
> 


__________________________________________________
Do you Yahoo!?
U2 on LAUNCH - Exclusive greatest hits videos
http://launch.yahoo.com/u2


From yapeter at stanford.edu  Thu Nov  7 08:34:28 2002
From: yapeter at stanford.edu (Yves-Alain Peter)
Date: Thu, 07 Nov 2002 08:34:28 -0800
Subject: chip curvature measurement?
References: <8B91B41B86B7D4118E390003470A02E3DC1B20@crum.internal.siliconlight.com>
Message-ID: <3DCA9613.E72B16F6@stanford.edu>

We have a ZYGO white light interferometer in the lab.

Contact Uli,

Yves-Alain

Omar Leung wrote:

>
>
> Sounds like you have a film membrane in a silicon frame?
>
> 1st are you sure the membrane will survive the dice?
> 2nd you are right, your chip will not have the same curvature as a
> unetched wafer.
>
> I would think the best way to measure such a structure in the lab
> would be to expand and collimate a laser beam, then measure the focal
> length. Alternately, you could put the laser on a micrometer stage and
> move it across your sample while you measure the position of the beam.
>
> This is essentially how the SMSI and Flexus machines work anyway.
>
> If you want more accurate results use a white light interferometer
> (Veeco/WYKO).
>
> Omar
>
> -----Original Message-----
> From: Yahong Yao [mailto:yy7343 at hotmail.com]
> Sent: Wednesday, November 06, 2002 4:38 PM
> To: labmembers at snf.stanford.edu
> Subject: chip curvature measurement?
>
> Dear Users,
>
> I am looking for a way to measure the curvature of a MEMS chip (size:
> 3mm*3mm*0.5mm).
>
> When we deposit films on one side of the Si wafer, due to the residue
> stress
> of the films the wafer bends.  It is easy to measure the curvature of
> the
> wafer by laser beam scanning.  If we dice the wafer into pieces
> (chips) as
> above size, how could we measure the curvature of the chips?  I think
> it
> might not be accurate to calculate the chip curvature according to the
> wafer
> curvature since the center of the chip is etched out, in another
> words, the
> remaining bulk Si part is just a frame (about 1/3 of the volume in
> center is
> etched away).
>
> Does any one know what tool and which company does this job?  Thanks
> in
> advance.
>
> Yahong
>
>
> _________________________________________________________________
> The new MSN 8: advanced junk mail protection and 2 months FREE*
> http://join.msn.com/?page=features/junkmail
>
>
> __________________________________________________
> The WebShield e500 Appliance has scanned
> this email message and attachments for viruses.
>
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From guerra at par.stanford.edu  Thu Nov  7 10:11:26 2002
From: guerra at par.stanford.edu (Ann Guerra)
Date: Thu, 7 Nov 2002 10:11:26 -0800 (PST)
Subject: EE310 Integrated Circuits Seminar, 11/12/02
Message-ID: <Pine.GSO.4.33.0211071007540.28328-100000@par.stanford.edu>

EE310 Integrated Circuits Technology and Design Seminar

"Microstrip Coupled VCOs for 40-GHz and 43-GHz OC-768
	  Optical Transmission"

	    Derek K. Shaeffer
	  Big Bear Networks, Inc.

	Tuesday, November 12, 2002
		4:15 p.m.
	 Building 380, Room 380X


		 ABSTRACT

The next frontier in high-speed optical fiber communications systems is
SONET OC-768, with transmission rates of 40Gb/s and higher.  These systems
produce one bit in the time required for light to travel about a quarter
inch.  Understandably, the timing jitter requirements placed on clock
sources in such systems are extreme.

In this talk, we examine the SONET jitter requirements for OC-768 systems
and explore techniques for implementing very low jitter oscillators using
coupled microstrips.  A novel prototype oscillator built according to the
techniques we develop exceeds SONET requirements with a phase noise of
-99dBc/Hz at 1-MHz carrier offset, consuming 363mW from a 3V supply.  This
oscillator is implemented in a 120-GHz fT SiGe BiCMOS process.



From afflannery at attbi.com  Thu Nov  7 11:12:27 2002
From: afflannery at attbi.com (Anthony Flannery)
Date: Thu, 7 Nov 2002 11:12:27 -0800
Subject: chip curvature measurement?
References: <8B91B41B86B7D4118E390003470A02E3DC1B20@crum.internal.siliconlight.com> <3DCA9613.E72B16F6@stanford.edu>
Message-ID: <004901c28691$9d10d0a0$8501a8c0@transparentnetworks.com>

The one drawback to the interferometer is that it has a relatively small field of view. I don't remember what it is off the top of my head, but I don't think this model has stitching so it's what you get looking through the scope. It'll give you localized deflections, but may not be big enough to give you curvature across the die. 

  ----- Original Message ----- 
  From: Yves-Alain Peter 
  To: Omar Leung 
  Cc: 'Yahong Yao' ; labmembers at snf.stanford.edu 
  Sent: Thursday, November 07, 2002 8:34 AM
  Subject: Re: chip curvature measurement?


  We have a ZYGO white light interferometer in the lab. 
  Contact Uli, 

  Yves-Alain 

  Omar Leung wrote: 

      
    Sounds like you have a film membrane in a silicon frame? 

    1st are you sure the membrane will survive the dice? 
    2nd you are right, your chip will not have the same curvature as a unetched wafer. 

    I would think the best way to measure such a structure in the lab would be to expand and collimate a laser beam, then measure the focal length. Alternately, you could put the laser on a micrometer stage and move it across your sample while you measure the position of the beam. 

    This is essentially how the SMSI and Flexus machines work anyway. 

    If you want more accurate results use a white light interferometer (Veeco/WYKO). 

    Omar 

    -----Original Message----- 
    From: Yahong Yao [mailto:yy7343 at hotmail.com] 
    Sent: Wednesday, November 06, 2002 4:38 PM 
    To: labmembers at snf.stanford.edu 
    Subject: chip curvature measurement? 

    Dear Users, 

    I am looking for a way to measure the curvature of a MEMS chip (size: 
    3mm*3mm*0.5mm). 

    When we deposit films on one side of the Si wafer, due to the residue stress 
    of the films the wafer bends.  It is easy to measure the curvature of the 
    wafer by laser beam scanning.  If we dice the wafer into pieces (chips) as 
    above size, how could we measure the curvature of the chips?  I think it 
    might not be accurate to calculate the chip curvature according to the wafer 
    curvature since the center of the chip is etched out, in another words, the 
    remaining bulk Si part is just a frame (about 1/3 of the volume in center is 
    etched away). 

    Does any one know what tool and which company does this job?  Thanks in 
    advance. 

    Yahong 
      

    _________________________________________________________________ 
    The new MSN 8: advanced junk mail protection and 2 months FREE* 
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From okilic at stanford.edu  Thu Nov  7 14:59:28 2002
From: okilic at stanford.edu (Onur Kilic)
Date: Thu, 7 Nov 2002 14:59:28 -0800 (PST)
Subject: Polishing
Message-ID: <Pine.LNX.4.44.0211071454340.17637-100000@cardinal3.Stanford.EDU>


I need to polish the backside of my wafers (Silicon). However, I cannot
use CMP since it is metal contaminated. I was thinking of doing resist
etchback to achieve a moderate quality polishing. Does anyone know a
receipe on the Drytek-2 that has no selectivity for silicon and resist, so
that I could do etchback polishing?

PS: It doesn't have to be on the Drytek.

Cheers,

ONUR KILIC

Graduate Student
Applied Physics
Stanford University

Tel: (650) 498 1371
Address: 750 Escondido Rd 138-B Stanford, CA 94305
Web: www.stanford.edu/~okilic




From rfasch at stanford.edu  Thu Nov  7 15:04:46 2002
From: rfasch at stanford.edu (rainer fasching)
Date: Thu, 7 Nov 2002 15:04:46 -0800
Subject: open C4  Prof.-position (Si-, micro-, nano- technology) Freiburg Universty  (germany)
Message-ID: <007e01c286b2$11345c20$7c7640ab@magician>

Hi all,
my former boss, now dean of the faculty of applied Sciences (Albert-Ludwigs-University Freiburg), is looking for candidates for a C4 Prof.-position in Si-technology, Nano-technology ...... at his University. Please check attached information sheet if you are interested in...
Thanks
Rainer

Rainer Fasching, Dr.
RPL_group
Phone>650.723.1301
Fax>650.723.5034
Email>rfasch at stanford.edu
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From jhannibal at snf.stanford.edu  Fri Nov  8 08:46:24 2002
From: jhannibal at snf.stanford.edu (Janine Hannibal)
Date: Fri, 08 Nov 2002 08:46:24 -0800
Subject: MORE WINNERS!
Message-ID: <3DCBEA60.8ACEF7F7@snf.stanford.edu>

CONGRATULATIONS to the additional winners of the SNF Survey Raffle. They
will receive a $10 gift certificate to BYTES Cafe located in the Packard
Building.

And the winners are...

wtpark
mehenti
yangxu
shimbo
jtsai

Please stop by my office to pick up your gift certificates!

If you have not already filled out a form and would like to do so, you can
find one here http://snf.stanford.edu/Labmembers/Survey.html.  Paper forms
can also be found outside the gowning room, behind the Coral terminals.
Surveys are always welcome!

We would like to thank you for your continued support of SNF. We appreciate
your comments and suggestions. Thank you!

Regards,

Janine Hannibal
Lab Services Administrator
Stanford Nanofabrication Facility
Phone 650-725-3664

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From shott at snf.stanford.edu  Tue Nov 12 11:03:40 2002
From: shott at snf.stanford.edu (John Shott)
Date: Tue, 12 Nov 2002 11:03:40 -0800
Subject: Coral inconsistency on Monday evening or Tuesday morning ...
Message-ID: <3DD1508C.AC1E337D@snf.stanford.edu>

SNF Lab Members:

Last evening, we had a period during which the Coral servers were not talking
with the database regarding equipment enables and disables.  As a result, who
currently has equipment enabled and equipment history may not be correct.  If
you were using equipment between about 9 p.m. last night and 9 a.m. this
morning, please check the equipment history records and the list of currently
enabled equipment.  If you notice an inconsistency, please send me the details
of what equipment you were using and start/stop times ... or any equipment
that may be enabled in the wrong name ... and I will make corrections.

While we had recently improved our ability to detect these problems
automatically, this failure had a different signature than we had seen
previously.  We are in the process of implementing 2 changes that should
reduce the likelihood of this problem recurring in the future:

1. We have just updated our detection/recovery mechanism to catch more of
these problems and to restart the servers as soon as we detect a problem.

2. Bill Murray has made some changes that, we beleive, will eliminnate these
communication failures completely.  We hope to install these changes within a
week ... along with a couple of new features that should be of interest to
you:

a. A new maintenance client that includes the full text (well, up to 4000
characters) of problem/shutdown messages and their resolution.

b. An alternative way of looking at equipment reservations so that you can see
all of your reservations (for all pieces of equipment) for a single day.

Stay tuned for details of these upcoming enhancements,

Thanks for your continued support ...

John


From curlwang at stanford.edu  Wed Nov 13 11:36:05 2002
From: curlwang at stanford.edu (Ke Wang)
Date: Wed, 13 Nov 2002 11:36:05 -0800 (PST)
Subject: ion sputterer
Message-ID: <Pine.GSO.4.44.0211131128210.27722-100000@elaine3.Stanford.EDU>

Dear lab people,

Many thanks for all the responses to mylar mask that I asked about last
time! And I have another question now. Does anybody know a place
on-campus that can do iron sputtering? My substrate is silicon.

Any clue is appreciated. Thanks!!

Ke

_____________________________________________
Ke Wang
PHD Candidate
Department of Applied Physics, Stanford University

CISX B113-14
Stanford, CA 94305-4070

Phone: (650)723-8040




From sarunyab at stanford.edu  Wed Nov 13 11:43:35 2002
From: sarunyab at stanford.edu (Sarunya Bangsaruntip)
Date: Wed, 13 Nov 2002 11:43:35 -0800
Subject: Seminar announcement: Melissa Hines, Cornell University. Nov 14 (Thu), 4:15 PM Braun Lecture Hall (Mudd Building).
Message-ID: <CAEJKOHGCBMGCPJMCOGCCEBOCGAA.sarunyab@stanford.edu>

Professor Melissa Hines, Cornell University. Nov 14 (Thu), 4:15 PM Braun
Lecture Hall (Mudd Building).

****************************************************************************
Adventures in Silicon Etching: From Atomic-Scale Chemistry to the Control of
Micromechanical Losses

Anisotropic etchants (etchants that selectively reveal specific
crystallographic faces) have long fascinated scientists. Decades before
x-ray diffraction was even imagined, mineralogists used anisotropic etchants
to reveal the inherent symmetry of crystals. In this talk, I will show that
under some circumstances, anisotropic etchants can be more precise and more
controlled than the most advanced microfabrication tools. In the first part
of this talk, I will use a combination of scanning tunneling microscopy and
atomistic simulations to study the atomic-scale reactions that lead to the
production of atomically flat (and atomically rough) etched surfaces. In the
second part of the talk, I will show how these highly selective chemical
etchants can be used to fabricate suspended resonators out of single crystal
silicon. More interestingly, this same chemistry can be used to control the
rate of mechanical energy dissipation in micromechanical devices. This
result suggests that careful attention to surface chemistry will be needed
for the development of high performance nanomechanical devices.

More about Professor Hines' work can be found at:
http://www.chem.cornell.edu/department/Faculty/Hines/hines.html
****************************************************************************



From rcrane at snf.stanford.edu  Wed Nov 13 17:30:38 2002
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Wed, 13 Nov 2002 17:30:38 -0800
Subject: Photo area disruption on Tuesday
Message-ID: <3DD2FCBE.EBCC8E46@snf.stanford.edu>

Fab users:

On Tuesday, November 19, the litho area and the measurement room
activities will be disrupted by equipment moves.

The Zygo profilometer will be moved into the measurement room around
0900-1000.

A  Nikon, body 9 aligner will be arriving around 1100. Insertion into
the litho area will be from 1100 to 1500? Since the temporary wall in
the corner of litho will be open for several hours, expect a higher
particle count in this area. Oven row (Blue-M and others) will not be
available for use during the move. After tool placement, the temporary
wall will go back up followed by reconstruction of the door frame and
wall.

Sorry for the disruption to your work,

Dick Crane



From guerra at par.stanford.edu  Thu Nov 14 11:33:42 2002
From: guerra at par.stanford.edu (Ann Guerra)
Date: Thu, 14 Nov 2002 11:33:42 -0800 (PST)
Subject: EE310 Integrated Circuits Seminar, 11/19/02
Message-ID: <Pine.GSO.4.33.0211141129170.12519-100000@par.stanford.edu>

EE310 Integrated Circuits Technology and Design Seminar

    "On-chip RF Isolation Techniques"

	    Tallis Blalack
	Cadence Design Systems


	Tuesday, November 19, 2002
		4:15 p.m.
	Building 380, Room 380X


		ABSTRACT

On-chip isolation is a function of many interdependent variables. This
talk will use industry examples to highlight isolation impacts of
substrate doping levels and triple wells, grounding schemes, guard
rings, shielding, capacitive decoupling and package inductance.




From gray at ee.Stanford.EDU  Thu Nov 14 12:57:05 2002
From: gray at ee.Stanford.EDU (Robert M. Gray)
Date: Thu, 14 Nov 2002 12:57:05 -0800
Subject: Special EE Seminar: Moore's Law
Message-ID: <200211142057.gAEKv5e09883@ee.Stanford.EDU>


EE Department Special Seminar

4PM Friday November 15
Packard 101

"Extending Moore's Law with Si Nanotechnology"

Scott List
Components Research
Technology and Manufacturing Group
Intel Corporation

Abstract

In 1965, Intel founder Gordon Moore first postulated his now famous 
projection that the number of transistors on an integrated circuit
would double every 18 to 24 months.  His forecast was based on four
years of data and expected to be valid for another ten years.  One
of the wonders of modern technology has been the ability of the 
semiconductor industry to continue this growth for 40 years by 
overcoming numerous, seemingly insurmountable barriers.  

This decade offers its own technological challenges including needs
for novel lithography sources and optics, atomic scale transistors,
advanced interconnect solutions and self-assembly processes.  While
these nanotechnology challenges are great, viable solutions have been
developed for these issues at least through the end of this decade 
with no fundamental barriers to the continuation of Moore's Law.  In
particular, researchers at Intel have recently published advances in 
EUV (13nm wavelength) lithography, 20 nm transistors with 3 atom thick
gate oxides, Cu/low k integration, transition to 300 mm wafers and 
high k and tri-gate transistor options.  These achievements not only
perpetuate Moore's Law, but also provide for continued reductions in
cost and extensions into wireless and optical communications.  Intel's
infrastructure and strategy for such research developments will also 
be described.

Speaker Bio:

Scott List received his BS degree in Applied and Engineering Physics
from Cornell University, and his PhD degree from the Applied Physics
Department at Stanford University with a dissertation on electrical and
structural properties of strained-layer heterojunctions.  After a
post-doctorial position at Los Alamos National Laboratories studying
high temperature superconductors, he joined Texas Instruments (TI) as a
member of the technical staff in 1990.  His research interests at TI
included the characterization of material defects in HgCdTe infrared
detectors and the integration of xerogel dielectrics into Si integrated
circuit interconnects.  In 1998, he joined Intel and is currently a
group leader exploring advanced interconnect solutions in the Components
Research Laboratory.  In addition, he leads the Intel's Strategic
Technology Roadmap Team evaluating technologies at and beyond the 45 nm
node.  Scott is a co-author of over 80 publications and 15 patent
applications.




From LCascao at genencor.com  Thu Nov 14 18:16:21 2002
From: LCascao at genencor.com (LCascao at genencor.com)
Date: Thu, 14 Nov 2002 18:16:21 -0800
Subject: Vibration Measurements
Message-ID: <OFF859867D.7E33CAF7-ON88256C72.000C1FF7-88256C72.000D3B70@genencor.com>

Hi

We are considering a room for an AFM and I need to assess it for vibration
levels.   The instrument must meet the specs of an E-beam or an SEM (BBN
Criterion D).  I was wondering if any labmember knew of a company that
could do such measurements.

Thanks,

Luis


-------------------------------------------------------
Luis G. Casc?o Pereira, Ph.D.
Scientist I
Genencor International
925 Page Mill Road
Palo Alto, CA 94304-1013
Tel: 650-846-7685
Fax: 650-621-8186
Mailto:Lcascao at genencor.com
-------------------------------------------------------



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From shott at snf.stanford.edu  Thu Nov 14 18:39:18 2002
From: shott at snf.stanford.edu (John Shott)
Date: Thu, 14 Nov 2002 18:39:18 -0800
Subject: Vibration Measurements
References: <OFF859867D.7E33CAF7-ON88256C72.000C1FF7-88256C72.000D3B70@genencor.com>
Message-ID: <3DD45E56.EEE709D4@snf.stanford.edu>

Luis:

In the past we have used two companies to do vibration, magnetic, and acoustic
measurements prior to siting vibration-sensitive equipment such as e-beam
tools and the like:

COLIN GORDON & ASSOCIATES
883 SNEATH LANE, SUITE 150
SAN BRUNO, CA  94066

VIBRATION ENGINEERING OCNSULTANTS
500 SEABRIGHT AVENUE, SUITE 101
SANTA CRUZ, CA  95062

While there are likely others in the Bay Area, these are the two that we have
used ...

Good luck,

John


From SamS at LSInc.biz  Fri Nov 15 15:36:05 2002
From: SamS at LSInc.biz (Samuel B. Schaevitz)
Date: Fri, 15 Nov 2002 15:36:05 -0800
Subject: High-temperature wafer/piece curvature measurement
Message-ID: <5.1.0.14.2.20021115143720.02b374e8@pop.lilliputiansystemsinc.com>

Hey All,

I want to measure the curvature of a wafer or piece in situ during thermal 
cycling. Ideally, I would like to be able to heat my wafer up to 900C.

I know that KLA-Tencor makes a machine (the FLX-2320) that can go up to 
500C, and they used to make machines (FLX-2400, 2900, 4100) that could go 
to 800-900C.

Does anyone know of a lab or company who has a system than can do this?

Thanks,
Sam

------------------------------------------------------
Samuel B. Schaevitz
Lilliputian Systems, Inc.
3-H Gill Street, Suite 200
Woburn, MA 01801

E-Mail: SamS at LSInc.biz
Mobile: (617) 543-5875



From bleen at stanford.edu  Mon Nov 18 10:41:15 2002
From: bleen at stanford.edu (J. Brian Leen)
Date: Mon, 18 Nov 2002 10:41:15 -0800
Subject: Quartz Etch Surface Uniformity
Message-ID: <HAELLLPJFCCIOKMKHHBMIEBOCAAA.bleen@stanford.edu>

Lab Members,
	I need to etch a large but shallow depression (~5mm x 5mm) in quartz.  The
depression should be only 40nm deep.  The item will be used as a substrate
for optical experiments so I am concerned about surface roughness in the
etched region.  I would like the RMS variation of this etch to be less than
5nm.  Is that possible with a 40nm etch?  Any ideas on what the best method
would be?  The wall profile is unimportant.
Thanks for any help,
	Brian
________________________
Brian Leen
bleen at stanford.edu



From shott at snf.stanford.edu  Mon Nov 18 14:09:23 2002
From: shott at snf.stanford.edu (John Shott)
Date: Mon, 18 Nov 2002 14:09:23 -0800
Subject: CIS 151 computers off the network!!!
Message-ID: <3DD96513.F930578D@snf.stanford.edu>

SNF Lab Members:

Because of security problems and excessive network traffic, all of the
computers in CIS 151 (including Shades and friends and the 2 PCs that are
often used for L-edit usage) have been removed from the network by order of
central campus network systems.  These machines will not be allowed back on
the network until we can demonstrate improved security related to their use. 
While I know that there are legitimate needs and uses for these machines ...
do not count on network access for the near term.  If we remove the PC
hardware completely, we may be able to return the Unix machines to the network
at an earlier date.  Folks may want to investigate getting and installing CD
R/W capabilities on the PCs in order to be able to use them for L-edit and for
getting files to appropriate lithography/mask making tools.

I apologize for this inconvenience ... but someone (not necessarily any of us
....) has turned these machines into bad network citizens.

If you have any specific comments, concerns, or suggestions please contact me
directly.

Thank you for your support,

John


From rcrane at snf.stanford.edu  Tue Nov 19 07:43:37 2002
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Tue, 19 Nov 2002 07:43:37 -0800
Subject: Photo area disruption today 11/19
Message-ID: <3DDA5C29.2D22D43F@snf.stanford.edu>

Fab users, just a reminder. Please note updated times.

Today, Tuesday, November 19, the litho area and the measurement room
activities will be disrupted by equipment moves.

The Zygo profilometer will be moved into the measurement room in the
afternoon.

A  Nikon, body 9 aligner will be arriving around 1200. Insertion into
the litho area will be from 1200 to 1600? Since the temporary wall in
the corner of litho will be open for several hours, expect a higher
particle count in this area. Oven row (Blue-M and others) will not be
available for use during the move. After tool placement, the temporary
wall will go back up followed by reconstruction of the door frame and
wall.

Sorry for the disruption to your work,

Dick Crane





From ibrahim at stanford.edu  Tue Nov 19 10:51:26 2002
From: ibrahim at stanford.edu (Nabeel Ibrahim)
Date: Tue, 19 Nov 2002 10:51:26 -0800 (PST)
Subject: Process/Device simulation on the leland system (was Re: CIS 151
 computers off the network!!!)
Message-ID: <Pine.GSO.4.44.0211191047570.18839-100000@epic18.Stanford.EDU>


For those of you who may use Medici, TSUPREM or other TMA tools on the
leland system:

Shades is the license server for those products.  Because Shades is down,
those simulation tools are now unusable on the leland system.

Nabeel

---------- Forwarded message ----------
Date: Mon, 18 Nov 2002 14:09:23 -0800
From: John Shott <shott at snf.stanford.edu>
To: labmembers at snf.stanford.edu
Subject: CIS 151 computers off the network!!!

SNF Lab Members:

Because of security problems and excessive network traffic, all of the
computers in CIS 151 (including Shades and friends and the 2 PCs that are
often used for L-edit usage) have been removed from the network by order of
central campus network systems.  These machines will not be allowed back on
the network until we can demonstrate improved security related to their use.
While I know that there are legitimate needs and uses for these machines ...
do not count on network access for the near term.  If we remove the PC
hardware completely, we may be able to return the Unix machines to the network
at an earlier date.  Folks may want to investigate getting and installing CD
R/W capabilities on the PCs in order to be able to use them for L-edit and for
getting files to appropriate lithography/mask making tools.

I apologize for this inconvenience ... but someone (not necessarily any of us
....) has turned these machines into bad network citizens.

If you have any specific comments, concerns, or suggestions please contact me
directly.

Thank you for your support,

John




From sylviajs at stanford.edu  Tue Nov 19 17:05:49 2002
From: sylviajs at stanford.edu (S. J. Smullin)
Date: Tue, 19 Nov 2002 17:05:49 -0800 (PST)
Subject: error in reticule calibration?
Message-ID: <Pine.GSO.4.44.0211191657480.943-100000@elaine15.Stanford.EDU>

I have been using the reticule on scope2 in the photolith room -- this is
the microscope across from the Nikon stepper and the reticule is the
little ruler in the eyepiece. On the base of the scope, there are
calibrations for the different objectives. I have been measuring mm-size
features using the objective labelled IC5. all evidence I have points to a
10% error in this calibration.

Has anyone noticed a similar error, or is there some conspiracy in the
making of my masks? Does anyone have a known-size thing they could use to
check these calibrations?


Sylvia Smullin

KGB Group
Physics Dept
Stanford University



From Jane.Edwards at stanford.edu  Wed Nov 20 09:56:11 2002
From: Jane.Edwards at stanford.edu (Jane Edwards)
Date: Wed, 20 Nov 2002 09:56:11 -0800
Subject: Message from Yoshio Nishi, SNF Director re: SNF rate increase
Message-ID: <FF1837A1813CF54F8A3579D3F46EB40FBAB834@ehost004.intermedia.net>

To: 	SNF Labmembers 
From:  	Yoshio Nishi, SNF Director

As many of you know, the SNF has had only one very modest rate increase
in 12 years and we have successfully maintained our present rates for
the past three years. However, due to increases in operating costs for
this facility and a larger equipment base, we are now forced to adjust
our rate structure. The new rate structure effective November 1, 2002 is
listed below:  

Stanford (or SLAC):	$75/hour (cap at $1600/month) + 58% overhead 

Other Academic:	$75/hour (cap at $1600/month) + 8% overhead 

Government/Industry:	$150/hour (cap at $3200/month) + 58% overhead 

While rate increases are never pleasant, rising costs have made this a
necessity at this time.  We do, however, have plans that will be
bringing more equipment and technology on-line during the coming year.
Additionally, we have also developed a set of plans that we feel will
result in overall increased equipment uptime and improved services to
our lab members.  We are hopeful that these positive elements will
justify the rate increases that we are now implementing.  More detailed
announcements of some of these changes will be forthcoming in the near
future.

We?d also like to take this opportunity to thank all of you who filled
out a User Survey. The feedback has been very helpful and has identified
areas for improvement in the lab.  If you haven?t completed a survey,
please feel free to send one to us.  It is critical for our successful
NNUN renewal that we get a high rate of returns on the survey.   Our
Advisory Board for NNUN has established a goal of an 80% response rate
to insure that we are listening to all of our lab members so your
feedback is extremely important to us.  The surveys can be found on our
website.  (http://snf.stanford.edu)

Should you have any questions related to our rate increases or our plans
for improved equipment uptime, please contact my Associate Director,
John Shott at shott at snf.stanford.edu.

Thank you for your continued support,

Yoshio Nishi
SNF Director




From shott at snf.stanford.edu  Wed Nov 20 10:56:07 2002
From: shott at snf.stanford.edu (John Shott)
Date: Wed, 20 Nov 2002 10:56:07 -0800
Subject: error in reticule calibration?
References: <Pine.GSO.4.44.0211191657480.943-100000@elaine15.Stanford.EDU>
Message-ID: <3DDBDAC7.C51EE8EC@snf.stanford.edu>

Sylvia:

Somewhere, we have a sample that has scribed lines at a known distance apart
... if my memory serves correctly, it has minor lines every 100 um and major
lines every 1.0mm (and maybe even a few lines 10um apart).  It used to live in
a little white case that said American Optical on it.  The case was big enough
to hold a microscope slide (say, 7 cm long, 3 cm deep and 1 cm high).  In the
old days, it used to live near the big Zeiss microscope in the sem room ...
but I can't find it in there now.

Has anyone seen this recently to know where it is now?

Note: I'm not sure that I'm surprised that you observe an apparent
magnification error of 10%.  Afterall, your calculations assume that the
magnification is exactly what is stamped either on the objective or on the
eyepiece.  While I don't know the specific tolerance to expect in our
inspection microscopes, my guess is that they are not perfect.  Since this
should not change with time (unless optics are exchanged, of course), we
should probably attempt to use the sample described above to measure the
magnification of our various microscopes.

Thanks,

John


From guerra at par.stanford.edu  Thu Nov 21 10:53:25 2002
From: guerra at par.stanford.edu (Ann Guerra)
Date: Thu, 21 Nov 2002 10:53:25 -0800 (PST)
Subject: EE310 Integrated Circuits Seminar, 11/26/02
Message-ID: <Pine.GSO.4.33.0211201110010.24047-100000@par.stanford.edu>

EE310 Integrated Circuits Technology and Design Seminar

"Wideband Analog-to-Digital Conversion Using Ultrafast Photoconductors
	Integrated with CMOS ADC Circuits"

      Lalitkumar Nathawad and Ryohei Urata
	     Stanford University

	  Tuesday, November 26, 2002
		  4:15 p.m.
	   Building 380, Room 380X




		    ABSTRACT

Conventional electronic analog-to-digital (A/D) converters are capable
of providing between 4 to 8 bits of resolution at a few GHz input
frequencies.  However, their performance is typically limited by the
bandwidth and distortion of the sample-and-hold circuit, as well as
timing jitter in the sampling clock.  Alternative photonic sampling
techniques are capable of offering much higher input bandwidths while
taking advantage of low-jitter mode-locked laser sources for precise
sampling times.

This work introduces a parallel ADC architecture in which a large
number of time-interleaved photonic-sampling channels each feed a
4-bit, 1-Gsample/s CMOS A/D converter.  Each channel samples the input
electrical signal using low-temperature-grown (LT) GaAs
photoconductive switches that are optically triggered by a 1-GHz
repetition rate short-pulse laser.  These switches provide a sampling
aperture of a few picoseconds with almost 6 bits of linearity and a
sampling bandwidth greater than 50GHz. The 4-bit CMOS A/D converter
used to digitize each of the sampled signals is constrained by the
need for a very low input capacitance and a small area, the latter
necessary to allow the integration of many converters on a single chip
to maximize the aggregate sampling rate. The use of optically
triggered sampling and interleaving relaxes the jitter, timing skew
and speed requirements of the electronic A/D converters.

A prototype two-channel 4-bit photonic-sampling A/D converter was
fabricated in 0.25um CMOS with flip-chip bonded LT GaAs switches.  The
converter provides a peak SNDR greater than 23dB for inputs up to
20GHz.  Each channel dissipates 70mW of power and occupies an active
area of 150um by 450um.








From jules83 at stanford.edu  Thu Nov 21 16:34:37 2002
From: jules83 at stanford.edu (Julia R Greer)
Date: Thu, 21 Nov 2002 16:34:37 -0800
Subject: Does Oxide stick to Gold?
Message-ID: <000a01c291be$f2dfc440$d37640ab@Touffler>

Hello fellow users,

I was wondering if anyone knew whether SiO2 adhered to Au films well or
not. If I wanted to CVD some of the oxide on top of my gold film, would
I need to use some sort of an adhesion promoter or is it going to stick
as-deposited?

Thank you!
-Julia

If you do not have 83,000 problems to worry about, it is not a stressful
day!


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From jlngau at stanford.edu  Thu Nov 21 19:04:05 2002
From: jlngau at stanford.edu (julie ngau)
Date: Thu, 21 Nov 2002 19:04:05 -0800 (PST)
Subject: Ph.D. Oral Examination Announcement -- Julie Ngau
Message-ID: <Pine.GSO.4.44.0211211859450.12216-101000@elaine19.Stanford.EDU>


               Special University Ph.D. Oral Examination

  Process Technology Development for Advanced Si Heterostructure Devices

                              Julie L. Ngau
             Department of Materials Science and Engineering
                           Stanford University

                Wednesday, November 27, 2002, 10:00 a.m.
    Center for Integrated Systems - Extension (CIS-X) Auditorium
                        Refreshments at 9:45 a.m.

                                Abstract

   Efforts in the semiconductor industry are continually directed towards
making faster and more economical integrated circuit (IC) chips with
greater functionality.  In order to achieve these goals, smaller
individual devices, nonplanar device structures, and heterostructure
materials are often incorporated into ICs.  Due to the challenges of
multi-dimensional design and heterostructure integration, many broad
technology issues are encountered throughout the fabrication process of
these innovative devices.  This work examines the two processes of
diffusion and oxidation in silicon and silicon germanium (SiGe)-based
heterostructures for advanced device application.  A combination of
experiments and process modeling has been used to investigate the
suppression of boron transient enhanced diffusion (TED) by carbon in Si
and SiGe, crystallographic orientation effects upon Si oxidation in a wet
ambient, and two-dimensional (2-D) oxidation of Si and SiGe
heterostructures.

   With the continued scaling of heterostructure devices to smaller
dimensions, TED is particularly important to understand and control
because of the often undesirable dopant redistribution that results from
it.  In this study, the time-evolved phenomena of B TED suppression by C
in Si and SiGe has been investigated and a comprehensive model of dopant,
point defect, and C interactions has been developed to successfully
simulate the experimental data.  With the advent of nonplanar device
configurations and shrinking minimum feature sizes, crystallographic
orientation effects upon the oxidation process become increasingly
significant.  The initial oxidation regime of (100), (110), and (111)
oriented Si in wet ambient has therefore been examined.  The results of
this work have demonstrated for the first time that rapid initial oxide
growth of Si(110) and an oxidation rate crossover of the (110) and (111)
planes exist for wet oxidation.  These anomalous phenomena have previously
been believed to be confined to dry oxidation.  It is known that 2-D
effects also have a significant impact upon the oxidation of small,
nonplanar structures due to oxidation retardation on curved surfaces
caused by stress and nonplanar oxide deformation.  In order to investigate
such effects further, thin oxides on Si and SiGe sub-micron cylindrical
pillars have been grown in wet and dry ambients.  The results have been
simulated and qualitative and quantitative observations have been made
comparing the stress-dependent oxidation of these materials.

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From shott at snf.stanford.edu  Fri Nov 22 07:37:01 2002
From: shott at snf.stanford.edu (John Shott)
Date: Fri, 22 Nov 2002 07:37:01 -0800
Subject: Does Oxide stick to Gold?
References: <000a01c291be$f2dfc440$d37640ab@Touffler>
Message-ID: <3DDE4F1D.2AAD8121@snf.stanford.edu>

Julia:

In general, gold doesn't adhere well to SiO2 ... although most of that
experience is related to getting a metal film of gold deposited onto oxide to
adhere.

As a rule of thumb, metals that oxidize readily, adhere well to SiO2. Aluminum
and titanium, for example, adhere very well.  Gold is probably the best
example of a metal that doesn't oxidize readily ... and doesn't adhere well to
SiO2.  When it is deposited onto SiO2, gold is almost always deposited onto a
thin "glue layer" of a metal such as chrome.

I'll see if I can dig up any technical references on this subject ... or
someone else may be able to quickly site an appropriate reference.

Good luck,

John


From Jdas at activeoptical.com  Fri Nov 22 12:24:54 2002
From: Jdas at activeoptical.com (John Das)
Date: Fri, 22 Nov 2002 12:24:54 -0800
Subject: Need of HF etch resistant Dielectric film 
Message-ID: <639B8C163707B3429AE22ACC0C3190B703FACA@newton.activeoptical.com>

Hi,

We are looking for some type of dielectric film that can be
evaporated/sputtered deposited[not spin on types] but are resistant to
Hydrofloric Acid type etchants.

Please let us know if such film exists, its source or any vendor who
might do the deposition for us.

Thank you very much for your help.

John Das

AON









From rcrane at snf.stanford.edu  Mon Nov 25 13:59:18 2002
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Mon, 25 Nov 2002 13:59:18 -0800
Subject: Christmas shut down 12/20
Message-ID: <3DE29D36.5A868447@snf.stanford.edu>

Labmembers,

It is that time of year again... time for our annual Christmas break
shut down. The lab will be closed to all users commencing at 0600 on
Friday December 20 and remain closed until 5:00PM, January 2, 2003. The
Innotec evaporator and AMTetch will be shut down starting Wednesday
December 18. Please schedule your processing needs accordingly. Personal
wafers and materials need to removed from the lab or placed in assigned
storage containers prior to the shut down.

Start up will commence at 0600 on Thursday, January 2, and the lab will
be open for use after 5:00PM. Some equipment may not be available for
use immediately use do to turn on failures. Equipment status reports
will be provided in the afternoon of the 2th. Please check the web site
for latest information. The Innotec will be down through January 8 to
accommodate its moving to a new location.

During the shut down vacuum pumps and process chambers are cleaned and
repaired, the fab is relamped, scrubbers are cleaned, toxic gas and wet
bench interlocks are tested, and the HV substation receives its four
year PM.

Thanks for your help,

Dick Crane



From mtang at snf.stanford.edu  Mon Nov 25 15:32:27 2002
From: mtang at snf.stanford.edu (Mary Tang)
Date: Mon, 25 Nov 2002 15:32:27 -0800
Subject: Annual Lab Cleanup!!
Message-ID: <3DE2B30B.50675683@snf.stanford.edu>

Dear Labmembers:

Just a reminder that another annual holiday tradition is nigh:  THE LAB
CLEANUP!!  Please, please help make this a cleaner, more organized place
to work by doing the following:

1.  Bunnysuits:  Please remove your bunnysuit when you think you'll be
done for the year.  (You can leave your hanger.)  All labmember
bunnysuits will be sent for cleaning at shutdown, so you may want to
remove personal items, like safety glasses, etc.

2.  Wafer boxes, cassettes, and other personal belongings:  Please
remove all personal belongings (namely, wafers and wafer boxes) that you
keep OUTSIDE of your personal bins by Monday, Dec. 16.  This is for the
safety/security of your materials (as there will be a lot of work done
in the lab over shutdown) as well as for neatness' sake. Ample storage
is available in the CAD room (provided your belongings are placed in a
personal bin with your name and the current date.)  If you plan on
continuing to work in the lab up until the bitter end, there will be red
dot stickers available in the gowning room, to mark your boxes as "work
in progress".  Starting Tues, Dec.17, any personal belongings found
outside of personal bins without red dot stickers will be removed from
the lab.  Anything with red dot stickers will be safe just until
shutdown.  By the way, in the new year, we'll be enforcing a policy
requiring that ALL cassette boxes be labeled with your Coral login and
current date (anything not labeled, or current -- as in a couple of
months -- may be subject to removal from the lab.  Sorry folks, but the
number of renegade wafer boxes is getting a wee bit out of hand... and a
label that just says "test wafers" is just simply not descriptive
enough...)

3.  Personal lab storage bins.  Labmembers who don't show any lab
activity over a period of three months (Sep-Nov) will be asked to give
up their personal storage bins.  Don't worry -- there will be plenty of
new bins available, if only we all use them only when we're active in
the lab.  (By the way, if you have a labmate who has left, and you still
need his/her things, please let us know and we can reassign the bin
space to you.)

Comments, questions or suggestions are appreciated --

Thanks,

Mary

--
Mary X. Tang, Ph.D.
National Nanofabrication Users' Network
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at snf.stanford.edu







From gray at ee.Stanford.EDU  Wed Nov 27 15:38:53 2002
From: gray at ee.Stanford.EDU (Robert M. Gray)
Date: Wed, 27 Nov 2002 15:38:53 -0800
Subject: Special Seminar
Message-ID: <200211272338.gARNcrA16438@ee.Stanford.EDU>


Dr. Jelena Kovacevic of Bell Labs (Lucent) will be visiting Stanford
December 3- December 5 and will be giving two special Seminars during
her visit. The Wednesday talk is intended for a more general audience.

     	    Life After Wavelets: The War Of The Frames
		     
		    Jelena Kovacevic, Bell Labs

             Tuesday, December 3rd Noon Packard 101

		    
			  ABSTRACT

The addition of wavelets to the signal processing toolbox greatly
enhanced our ability to deal with nonstationary signals. Its effects
are felt beyond the research community through JPEG, now wavelet
based.

Frames -- redundant representations of which wavelets are a subclass
-- are the next addition to the toolbox. Tight frames, in particular,
with a few restrictions, become orthonormal bases. I talk here about
finite tight frames, fundamental for a broad spectrum of applications.
Until now it was thought that such frames were sparse.  I show that
actually tight frames are everywhere and they can be custom built for
most applications as long as the requirements are not too rigid and do
not violate the Fundamental Inequality which all tight frames must
satisfy. This inequality governs the distribution of power among the
frame vectors. In this ``war of the frames'', if the Fundamental
Inequality is not satisfied, the dominant vectors grab dimensions to
themselves and let the rest of the vectors squabble over the remaining
dimensions. On the other hand, if the Fundamental Inequality holds, no
vector is powerful enough to subjugate the rest, leading to equitable
power sharing.


			Photo-to-Grandma Problem:
			Compression Meets the Network

			Jelena Kovacevic, Bell Labs

                  Wednesday, December 4th  4:15p.m  Packard 176

In communications, separating source coding from channel coding is a
standard form of modularization. It makes things simple for us, and
furthermore Shannon's Separation Principle allows us to feel that we
are not going to suffer for it. For practical purposes, separation
leads to big toolboxes of reusable tools.

I'll examine certain communication scenarios and draw conclusion on
the existing toolboxes. I'll show that there is life beyond
multiresolution.  In particular, in some communication scenarios, the
information available at the source decoder is a subset of a small
number of chunks of data. Then, the right tools for source coding are
not the conventional ones, but rather multiple description codes. I'll
conclude with demonstrations of multiple description speech and audio
coders.



From guerra at par.stanford.edu  Wed Nov 27 17:32:16 2002
From: guerra at par.stanford.edu (Ann Guerra)
Date: Wed, 27 Nov 2002 17:32:16 -0800 (PST)
Subject: EE310 Integrated Circuits Seminar, 12/3/02
Message-ID: <Pine.GSO.4.33.0211271724080.8590-100000@par.stanford.edu>

EE310 Integrated Circuits Technology and Design Seminar

"Divide the Evil! or: How to Stop Worrying
  and Make Better Distributed Circuits"

	    Ali Hajimiri
Department of Electrical Engineering
 California Institute of Technology


     Tuesday, December 3, 2002
	    4:15 p.m.
      Building 380, Room 380X


		 ABSTRACT

While traditional integrated circuit design has triumphed over the last
two decades, it is reaching some of its limitations very quickly, as the
frequencies go up, breakdown voltages go down, and batteries become
smaller. At the same time, it is very desirable to use high-volume silicon
based technologies (e.g., CMOS) to achieve more bandwidth, higher
efficiency, and lower noise, at a very small cost.

In this talk, we present new approaches to distributed circuit design that
offer attractive alternatives to the traditional methods offering novel
solutions to some of the more challenging and often self-contradictory
requirements of high-speed communication integrated-circuit design.
Distributed circuit design is a multi-level approach allowing a more
integral co-design of the building blocks at the circuit and device
levels. It relies on multiple parallel signal paths operating in harmony
to achieve the specified design objectives.

In particular, we demonstrate distributed building blocks, such as voltage
controlled oscillators and watt-level fully-integrated CMOS power
amplifiers achieving unprecedented performance using this multiple signal
path approach. We will also demonstrate the new concept of concurrent
transceivers as another way of using multiple distributed paths to achieve
simultaneous operation at various frequencies.

As a side bonus, a theoretical treatment of the fundamental performance
limits of integrated passive components will be presented that will lead
to new capacitor structures with larger capacitance densities, higher
self-resonance frequencies, and superior matching properties compared to
the all previously-reported lateral-field capacitors, including special
thin dielectric MIMs.