From pindermuhle at zyomyx.com Tue Oct 1 08:08:39 2002 From: pindermuhle at zyomyx.com (Indermuhle, Pierre) Date: Tue, 1 Oct 2002 08:08:39 -0700 Subject: Cr etch Message-ID: <481EAD19D8B3E74687E11E31AD988CC404EB50@tahoe.zyomyx.com> Good morning I need to ecth a 50 Aengstroems thick layer of Cr (adhesion layer for a 1000 A thick gold layer). Does anybody have some Cr14, which I could use? Thanks a lot Pierre Pierre-F. Indermuhle Research Scientist ZYOMYX 3911 Trust Way Hayward, CA 94545 http://www.zyomyx.com Phone: (510) 266-7509 Fax: (510) 786-3832 PIndermu at zyomyx.com From pindermuhle at zyomyx.com Tue Oct 1 08:14:24 2002 From: pindermuhle at zyomyx.com (Indermuhle, Pierre) Date: Tue, 1 Oct 2002 08:14:24 -0700 Subject: Cr etch Message-ID: <481EAD19D8B3E74687E11E31AD988CC404EB52@tahoe.zyomyx.com> Good morning I need to ecth a 50 Aengstroems thick layer of Cr (adhesion layer for a 1000 A thick gold layer). Does anybody have some Cr14, which I could use? Thanks a lot Pierre I'm sending this e-mail again, since I'm not sure if it went through properly. Sorry for the redundancy... Pierre-F. Indermuhle Research Scientist ZYOMYX 3911 Trust Way Hayward, CA 94545 http://www.zyomyx.com Phone: (510) 266-7509 Fax: (510) 786-3832 PIndermu at zyomyx.com From Jane.Edwards at stanford.edu Tue Oct 1 09:31:14 2002 From: Jane.Edwards at stanford.edu (Jane Edwards) Date: Tue, 1 Oct 2002 09:31:14 -0700 Subject: SNF Labmember Survey Message-ID: SNF Labmember Survey Dear Labmembers: Your friendly neighborhood SNF staff and faculty Advisory Committee, on behalf of the National Science Foundation, are asking for your help in providing feedback about our lab. In addition to satisfying the NSF reporting requirement, the survey results will be used by the staff and the Advisory Committee to set the agenda and priorities for the lab. Your honest, constructive feedback is valued. In order to encourage feedback (NSF requires that we provide a 75% response rate), labmembers who return survey forms will be automatically entered into a drawing for a free lunch at Bytes cafe. The 10 lucky labmembers, picked at random, will be notified by email by 10/18/02. Blank survey forms will be available outside the lab entrance and online at the SNF website (http://snf.stanford.edu). PDF and Word versions of the forms are also attached to this email or in text form at the bottom of this email. Forms may be returned to the labeled box outside the lab entrance or by mail to: Labmember Survey Attn: Jane Edwards CIS Room 130, Mail code 4070 jane.edwards at stanford.edu Stanford University Stanford, CA. 94305-4075 Please return responses by 10/15/02. Responses will then be tabulated and summarized for all labmembers to review. Thank you for your help, On behalf of NSF, the SNF Staff and Advisory Committee _________________________________________ SNF LABMEMBER SURVEY 2002 I. YOUR USE OF THE LAB 1. Are you a PI? ___Yes ___No (If yes, please skip to section II.) 2. Your Coral login _____________________ 3. How long have you been using the SNF? ____________________ 4. Which of the following best describes your personal use of the lab? (Please choose one) ___ Occasional (less than 8 hours/month) ___ Light (8-32 hours/month) ___ Moderate (32-64 hours/month) ___ Heavy (64-160 hours/month) ___ Live there (>160 hours/month) 5. What is the general complexity of your devices? _________ # mask layers _________ critical line width dimension _________ critical alignment tolerance 6. What substrates do you use? (Check all that apply) ___ Silicon ___ GaAs ___ Quartz/fused silica ___ Glass/Pyrex ___ Sapphire ___ Other (describe) ______________________ 7. What substrate size do you usually use? (Check all that apply) ___ 2" ___ 3" ___ 4" ___ 5" ___ 6" ___ pieces ___ other(describe) _______________ 8. What are your contamination control requirement for your project? (Check all that apply) ___ CMOS clean ___ Standard Metal-compatible ___ Nonstandard (Gold and alkali metals acceptable) 9. Please rate the following on a scale from 1 to 5: (1=Poor; 5= Excellent; NA= Not applicable). Facility preparation for your visit Staff support Adequacy of training Quality of the equipment resource Adequacy of the equipment resources to your needs Accessibility of equipment Achievement of your expectations Value received for your expense Overall effectiveness of the program II. YOUR RESEARCH 1. What is your Labmember Category (choose one): ___ Stanford University ___ Non-Stanford Academic ___ Industry/Government ___ Other (describe) ______________________ 2. Please choose one of the following NSF categories to describe the general area of your research: ___ Electronics/semiconductor devices ___ Process Characterization ___ Physics ___ Biology ___ Chemistry ___ MEMS ___ Optics ___ Materials 3. Please choose those categories which describe your research (check any and all that apply): ___ NANOSCIENCE & TECHNOLOGY ___ NANOSTRUCTURED MATERIALS ___ NANOELECTRONICS ___ SENSORS ___ ELECTRONICS ___ PROCESS DESIGN ___ MATERIALS ___ STRUCTURES ___ BIOLOGY ___ BIOMEDICAL/BIOANALYTICAL ___ BASIC CELL/MOLECULAR BIOLOGY ___ BIOMIMETICS ___ PHOTONICS ___ OPTICAL PHYSICS ___ OPTICAL MEMS ___ MATERIALS/PASSIVE STRUCTURES ___ ELECTROOPTICS ___ OTHER: ___ MICROFLUIDICS ___ APPLIED PHYSICS ___ CIVIL ENGINEERING/GEOLOGY ___ SURFACE SCIENCE ___ POLYMER CHEMISTRY ___ SENSORS ___ PACKAGING ___ OTHER (describe):___________ III. WHERE WOULD YOU LIKE SEE THE LAB TO GO? 1. What do you see as the SIX most critical tools in the lab for your research? (Please rank.) 2. What kind of modifications or improvements would you like to see in thess or other equipment? 3. What new equipment, tools or processes would you like to see in the lab? -------------- next part -------------- A non-text attachment was scrubbed... Name: Survey.doc Type: application/msword Size: 31744 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Survey.pdf Type: application/pdf Size: 366907 bytes Desc: not available URL: From igregoratto at neophotonics.com Wed Oct 2 13:23:54 2002 From: igregoratto at neophotonics.com (Ivano Gregoratto) Date: Wed, 2 Oct 2002 13:23:54 -0700 Subject: Temperature dots ?? Message-ID: <363C5E09A79868448D9D4BC7E5FA8BFF65FAD0@NGM06> Hi everyone, I'm looking for some Temperature Dots that I can use to monitor the maximum temperature reached in an etch system. (typical range from 60-130 degrees C) Can anyone point me to any local vendors that would have these temp dots ? Thanks, ivano From mbadi at relgyro.stanford.edu Wed Oct 2 22:42:37 2002 From: mbadi at relgyro.stanford.edu (Mohammed H. Badi) Date: Wed, 2 Oct 2002 22:42:37 -0700 (PDT) Subject: Recruiting Event For Fab in Edmonton Message-ID: Hey all, A brand new fabrication facility is being built in Edmonton, Alberta, and they need people to work there! Better yet, they'll be coming to CIS on Thursday, October 17, 2002 at 6pm to meet with YOU. There will be an information session in the CIS courtyard to discuss the opportunities available. Briefly, Canada's National Institute For Nanotechnology (NINT) is based out of the Univesity of Alberta and is funded by Canada's National Research Council (NRC), Alberta Innovation and Science, and the University of Alberta. The NINT people are planning on hiring over 700 people in the next five years and are interested in meeting students and professionals in a number of disciplines. Dinner will be provided (yes, that gets its own paragraph). Check out the Stanford Canadian Club website for more information (http://www.stanford.edu/group/cdnclub). If you have any questions, please direct them to David Antoniuk (david.antoniuk at gov.ab.ca or 780.427.6618). Mohammed Badi mbadi at snf -------- Mohammed H. Badi 650.906.0663 From mtang at snf.stanford.edu Thu Oct 3 08:54:32 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Thu, 03 Oct 2002 08:54:32 -0700 Subject: Labmember Survey! Message-ID: <3D9C6838.4D150677@snf.stanford.edu> Greetings Labmembers -- As the less-than-competent webmaster, I have neglected a few key facts and now want to clarify a couple of points about the electronic versions of the Labmember Survey.... If you have Adobe Reader (the freebie plugin), you can't save the PDF file, but you can view, fill-in and print it. So, please provide us with a hard copy (which you can hand in or fax to (650)725-6278). If you are lucky enough to have Adobe Acrobat (the software you have to pay for, well, generally), then you can view, fill-in, save, and then email back the completed PDF as an attachment. However, I think you have to do this within Adobe Acrobat, itself -- if you do this through your browser, chances are it won't actually save your entries (although you'll think it has) and you'll be sending us a blank form. If you'd rather not hassle with PDF at all, the text file is also available on the SNF website. Just cut and paste into your favorite email editor and go! By the way, MANY thanks to those of you who have already turned in surveys (you probably have already done your taxes too) -- your support in assembling our annual report to NSF is greatly appreciated! For those of you who haven't -- please, please keep them coming in -- we're getting lots, but are nowhere yet near the 75% required by NSF! Regards, Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From guerra at par.stanford.edu Thu Oct 3 18:36:32 2002 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 3 Oct 2002 18:36:32 -0700 (PDT) Subject: EE310 Integrated Circuits Seminar, 10/8/02 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Circuit Techniques for a Monolithic Cartesian Feedback Power Amplifier System" Joel Dawson Stanford University Tuesday, October 8, 2002 4:15 p.m. Building 380, Room 380X ABSTRACT Designers of RF power amplifiers (PAs) for modern wireless systems are faced with a difficult tradeoff. On one hand, the PA consumes the lion's share of the power budget in most transceivers; it follows that in a cellular phone, for example, battery lifetime is largely determined by the power efficiency of the PA. On the other hand, it may be desirable to have high spectral efficiency - the ability to transmit data at the highest possible rate for a given channel bandwidth. The design conflict is that while spectral efficiency demands a highly linear PA, power efficiency is maximized when a PA is run as a constant-envelope, nonlinear element. The current state of the art is to design a moderately linear PA and employ some linearization technique. The amplifier is run as close to saturation as possible, maximizing its power efficiency, and the linearization system maximizes the spectral efficiency in this near-saturated region. There are many different linearization techniques. Our work has focused on Cartesian feedback systems for two main reasons: 1) because they employ analog feedback, the requirement for a detailed nonlinear model of the PA is greatly relaxed; 2) they automatically and elegantly compensate for process variations, temperature fluctuations, and aging. Nevertheless, historically the technique has suffered the practical shortcoming of relying on synchronous downconversion, which has been difficult to ensure without manual trimming. This problem, combined with the recent trend toward fully monolithic systems, has caused Cartesian feedback to languish for years as little more than an academic curiosity. We have solved the synchronous downconversion problem with a new, nonlinear, analog phase alignment regulator. What this enables, for the first time, is a fully integrated Cartesian feedback system that can function with an absolute minimum of trimming. A prototype IC, complete with power amplifier, phase alignment regulator, and Cartesian feedback circuitry, will be the focus of this presentation. The IC was fabricated in National's 0.25um process. From opticalmachine at hotmail.com Sun Oct 6 21:34:28 2002 From: opticalmachine at hotmail.com (Ben Jian) Date: Sun, 6 Oct 2002 21:34:28 -0700 Subject: patterning silicon nitride Message-ID: Hi, I am trying to pattern 1700 A of LPCVD nitride on a silicon wafer. The features are 450 micron size. The nitride etch process should not etch silicon surface at all. Does anyone have a process for it? I am thinking about using hot phosphoric acid to etch nitride without etching silicon at all. But what should be the etch mask during phosphoric etch? Thanks for your help. Ben -------------- next part -------------- An HTML attachment was scrubbed... URL: From mwolfson at exajoule.com Mon Oct 7 11:41:22 2002 From: mwolfson at exajoule.com (Michael Wolfson) Date: Mon, 7 Oct 2002 11:41:22 -0700 Subject: Anyone with polyimide experience? Message-ID: <000d01c26e31$24e5d490$0601000a@EXAJ005> Howdy, I'm trying to create a sacrificial layer for metal deposition. I'll need to be able to clear the sacrificial material from under a 2 um high, 11 um long plate. All indications point to polyimide, which I've never used before. I'd appreciate hearing from anyone with experience spinning, patterning, and removing it. Thanks in advance, -- Michael Wolfson From SamS at LSInc.biz Mon Oct 7 14:43:10 2002 From: SamS at LSInc.biz (Samuel_B_Schaevitz) Date: Mon, 7 Oct 2002 14:43:10 -0700 Subject: 1x10 micron trenches in Si Message-ID: <3DA1C54600000607@mta07.san.yahoo.com> Hey All, I would like to etch 10 micron deep, 1 micron wide trenches into a wafer. Has anyone done anything like this before? Thanks, Sam ------------------------------------------------------ Samuel B. Schaevitz Lilliputian Systems, Inc. 6 Keenan Drive Winchester, MA 01890 E-Mail: SamS at LSInc.biz Mobile: (617) 543-5875 From mahnaz at snf.stanford.edu Wed Oct 9 11:03:27 2002 From: mahnaz at snf.stanford.edu (Mahnaz) Date: Wed, 09 Oct 2002 11:03:27 -0700 Subject: DUV -248 nm Message-ID: <3DA46F6F.392F0312@snf.stanford.edu> Hello all, It is my pleasure to let you know that there will be a class on DUV-248 nm on Thursday 10/24/02 at 2 pm in Auditorium in CIS extension. The class will be given by Dr. Frank Yaghmaie of shipley and will cover: Short discussion of I- line resist DUV-248 nm lithography. Material aspects of polymers, photo acid generators, quenchers and what type of solvents used for 248 nm resists. Families of DUV resists, high and low activation formulations. Bi- layer lithography. use of bottom anti reflective coating. Let me know if you like any other topic to be discuss at this class and I will pass it down to Dr. Yaghmaie. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Wed Oct 9 13:29:25 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 09 Oct 2002 13:29:25 -0700 Subject: Get your surveys in!!! Message-ID: <3DA491A5.BC0F790@snf.stanford.edu> Greetings Labmembers! We've got a bunch of surveys in (thanks!) and the feedback so far has been interesting and helpful... However, we are a loooong way away from attaining the NSF goal of 75% user feedback. As we are approaching our last year of NSF funding and hoping for renewal for next year, it is extremely important that we make every attempt to achieve this and the many other goals set forth by NSF. Isn't the financial future and national reputation of the Stanford Nanofab (not to mention, a chance of free lunch at Joe & Jill's) worth a few minutes of your time? Please, please, please send in your surveys! Thanks for your time -- Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From shott at snf.stanford.edu Thu Oct 10 17:12:44 2002 From: shott at snf.stanford.edu (John Shott) Date: Thu, 10 Oct 2002 17:12:44 -0700 Subject: Strange hourglass behavior on SunRays ... Message-ID: <3DA6177C.4E6E5483@snf.stanford.edu> SNF Lab Members: Several of you have pointed out the strange "hourglass" behavior that you have been observing occasionally when you insert or extract smart cards into the sunrays. While we don't know the exact cause of this problem (although it isn't related to Coral ....) we would like to take the system down early tomorrow morning to apply some operating system patches. We are hopeful that this may improve this hourglass problem ... but we have also been hoping to apply some of these patches anyhow because we have wanted to minimally affect lab operations. We hope to get this started by 6 a.m. tomorrow morning with the expectation that the system (including Coral) will be fully operational again before 8 a.m. Thanks for your cooperation, John From mtang at snf.stanford.edu Mon Oct 14 14:32:37 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Mon, 14 Oct 2002 14:32:37 -0700 Subject: Surveys!!! Message-ID: <3DAB37F5.40E9B728@snf.stanford.edu> Greetings all!! Last chance to get your surveys in!! They are due in tomorrow (Tuesday). Of course, we'll continue to accept survey forms as long you'd like to return them, but eligibility for the drawing ends tomorrow, so get them in soon, please!! Just a reminder: paper forms can be found outside the gowning room, behind the Coral terminals. Forms are also available on the web at http://snf.stanford.edu/Labmembers/Survey.html Thanks!!! (Especially to those folks who've already turned theirs in!) Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From guerra at par.stanford.edu Mon Oct 14 22:06:38 2002 From: guerra at par.stanford.edu (Ann Guerra) Date: Mon, 14 Oct 2002 22:06:38 -0700 (PDT) Subject: EE310 Integrated Circuits Seminar, 10/15/02 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Design Tradeoffs for Continuous Phase Modulation: Capacity Bounds vs.Linearity and Power Backoff" Kevin Yu Stanford University Tuesday, October 15, 2002 4:15 p.m. Building 380, Room 380X ABSTRACT Modern communications demands smaller, cheaper, more portable devices capable of higher communication rates. Thus, integration technologies such as CMOS are very appealing. Integration, however, requires the analog transmitter and receiver devices to be designed in CMOS technology. Linearity of the final power amplifier is difficult to achieve with small power budgets. Furthermore, highly inefficient power amplifiers imply lower battery lifetimes and larger heat dissipation. Traditionally, linear modulation techniques are used due to their higher capacity. Furthermore, error correction coding is well studied for linear modulation techniques. However, a class of constant envelope nonlinear modulation techniques exist which are conducive to implementation in CMOS. However, due to their nonlinear nature, understanding of coding and even fundamental information capacity are not well understood. In this talk, we will discuss the basic ideas of nonlinear modulation using Continuous Phase Modulation (CPM). We examine the difficulties in analysis caused by the nonlinearity of the CPM. We will derive upper bounds on the capacity of an additive white Gaussian noise channel using Continuous Phase Modulation and propose some coding methods which may achieve near capacity performance. To derive the capacity bounds, we propose using an arbitrary number of linear, filtered pulses to form an MMSE approximation to Laurent's linear decomposition of arbitrary binary input CPM. Using this decomposition and approximation, the capacity bounds in white and colored Gaussian noise is derived by showing the system is equivalent to a multiple antenna channel with intersymbol interference (ISI). The capacity of such a channel is used as the upper bound. Furthermore, we use this decomposition and approximation to derive some design insights for the power backoff needed in the power amplifier. Numerical results are presented for a channel using CPM with both white and colored noise. The bounds show a significant gap between a channel using CPM and a channel with unconstrained modulation. From estraver at stanford.edu Tue Oct 15 17:41:18 2002 From: estraver at stanford.edu (Eric Straver) Date: Tue, 15 Oct 2002 17:41:18 -0700 (PDT) Subject: [REMINDER] Information Session For Fab in Edmonton Message-ID: Hi, Just a reminder, the National Institute for Nanotechnology in Edmonton, Alberta will be holding an information session on Thursday. Details are in the original message, included below. Whether you're interested in employment, a collaboration, or just knowing what's going on there, please come to the CIS courtyard at 6pm. Dinner will be provided and there will be door prizes as well; please RSVP to Michael Ede (ede at pobox.com). Resumes will be accepted. ---------------------- Hey all, A brand new fabrication facility is being built in Edmonton, Alberta, and they need people to work there! Better yet, they'll be coming to CIS on Thursday, October 17, 2002 at 6pm to meet with YOU. There will be an information session in the CIS courtyard to discuss the opportunities available. Briefly, Canada's National Institute For Nanotechnology (NINT) is based out of the Univesity of Alberta and is funded by Canada's National Research Council (NRC), Alberta Innovation and Science, and the University of Alberta. The NINT people are planning on hiring over 700 people in the next five years and are interested in meeting students and professionals in a number of disciplines. Dinner will be provided (yes, that gets its own paragraph). Check out the Stanford Canadian Club website for more information (http://www.stanford.edu/group/cdnclub). If you have any questions, please direct them to David Antoniuk (david.antoniuk at gov.ab.ca or 780.427.6618). From beckwith at snf.stanford.edu Wed Oct 16 16:59:19 2002 From: beckwith at snf.stanford.edu (Sharleen Beckwith) Date: Wed, 16 Oct 2002 16:59:19 -0700 Subject: outside source for SiGe (30% Ge) on Si? Message-ID: It seems the snf epi reactor will be down for a "month or so". Does anyone have any good outside sources for epi? We are working on 4" wafers. Thanks. Sharleen -- "To announce that there must be no criticism of the president, or that we are to stand by the president right or wrong, is not only unpatriotic and servile, but is morally treasonable to the American public." Theodore Roosevelt writing in the Kansas City Star May 7, 1918 -- From rcrane at snf.stanford.edu Thu Oct 17 10:11:09 2002 From: rcrane at snf.stanford.edu (Dick Crane) Date: Thu, 17 Oct 2002 10:11:09 -0700 Subject: EPI reactor References: Message-ID: <3DAEEF2D.D1A18246@snf.stanford.edu> Labmembers: Please disregard the attached e-mail. The epi reactor is NOT scheduled for any down time in the foreseeable future. It is certainly NOT going to be down a "month or so". Thanks, Dick Lab Operations Manager Sharleen Beckwith wrote: > It seems the snf epi reactor will be down for a "month or so". Does > anyone have any good outside sources for epi? We are working on 4" > wafers. > > Thanks. > > Sharleen > -- > "To announce that there must be no criticism of the president, > or that we are to stand by the president right or wrong, > is not only unpatriotic and servile, > but is morally treasonable to the American public." > > Theodore Roosevelt > writing in the Kansas City Star > May 7, 1918 > -- From guerra at par.stanford.edu Thu Oct 17 11:10:21 2002 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 17 Oct 2002 11:10:21 -0700 (PDT) Subject: EE310 Integrated Circuits Seminar, 10/22/02 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Electronics for the Large-Area Telescope for the GLAST Space Mission" Gunther Haller Stanford Linear Accelerator Center Stanford University Tuesday, October 22, 2002 4:15 p.m. Building 380, Room 380X ABSTRACT GLAST is a next generation $500-Million high-energy gamma-ray space-based observatory designed for making observations of celestial gamma-ray sources in the energy band extending from 10 MeV to more than 100 GeV. It is scheduled to be launched in 2006 on a Delta II rocket. The Large Area Telescope (LAT) consists of ~800,000 channels of silicon-strip detectors to track particles, calorimeter detectors to measure the deposited energy of the particles, and scintillator detectors to provide cosmic-ray rejection. Electronics for the LAT contains several mixed-signal custom integrated circuits. The seminar will give an overview of the LAT instrument with a description of the electronics. The signal-processing integrated circuits being developed to read-out high-energy physics-type detectors are reviewed. Challenges are low-noise, low-power, and operation in space-environment. BIOGRAPHY Gunther Haller received the M.S. and Ph.D in electrical engineering from Stanford University in 1990 and 1994, respectively. He is the head of the Electronics and DAQ department of the SLAC research division. Gunther is also the chief-electronics engineer of the NASA/DOE Gamma-Ray Large Telescope. From lkam at STANFORD.EDU Thu Oct 17 11:50:18 2002 From: lkam at STANFORD.EDU (Lance Kam) Date: Thu, 17 Oct 2002 11:50:18 -0700 Subject: Ge ATR crystal with SiO2 Message-ID: <3DAF066A.3DBEDCC7@STANFORD.EDU> Hello all- Can anyone share experience on coating germanium with SiO2? The trick here is that this structure has to be stable under water; no strong acids or bases, but salts on the order of 100-200 mM. >From hunting around the literature, my best guess at a process is to, in a PECVD: 1) remove the native Ge oxide using a hydrogen etch 2) deposit a thin layer (~1nm) of Si 3) deposit SiO2 (~20nm) Aside from not being able to do a hydrogen plasma etch at the SNF, are there other pitfalls and/or alternatives that come to mind? Thanks in advance, Lance From jhannibal at snf.stanford.edu Fri Oct 18 14:52:15 2002 From: jhannibal at snf.stanford.edu (Janine Hannibal) Date: Fri, 18 Oct 2002 14:52:15 -0700 Subject: We have WINNERS!!! Message-ID: <3DB0828F.D32B6E08@snf.stanford.edu> CONGRATULATIONS! The following SNF Survey Winners will each receive a $10.00 gift certificate to Stanford's world famous BYTES Cafe located in the Packard building. The Winners are: rajesh farhat lwpan auber gu wittbrod gigi qwang ehkim trevor (Please see me to claim your certificate.) THERE'S ONE MORE CHANCE TO WIN! We are still accepting surveys! Please either email or hand in your survey to me. The next drawing for gift certificates will be held on Thursday, OCTOBER 31st. (If you've already handed in your survey, you are still eligible to win.) DON'T MISS OUT! Get your surveys to me as soon as you can! Thanks for all your cooperation! -- Janine Hannibal Lab Services Administrator Stanford Nanofabrication Facility Room 41 Phone 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From hlkung at stanford.edu Sun Oct 20 16:18:23 2002 From: hlkung at stanford.edu (Helen L. Kung) Date: Sun, 20 Oct 2002 16:18:23 -0700 Subject: Helen Kung - Ph.D. Oral Examination Message-ID: <5.1.1.5.2.20021020161109.00afc658@hlkung.pobox.stanford.edu> ************************************************************************ University Ph.D. Oral Examination Miniature optical wavelength sensors Helen L. Kung Department of Electrical Engineering Stanford University CIS-X auditorium Thursday, October 24th, 2002 9:00 AM-10:00 AM (Refreshments served at 8:45 AM) ************************************************************* Recent semiconductor processing technology has been applied to the miniaturization of optical wavelength sensors. Compact spectral sensors could enable new applications such as wavelength monitors integrated with diode-lasers, portable chemical and biological detection, and mobile hyperspectral imaging arrays. We have investigated existing designs and developed novel architectures for wavelength sensing. Many traditional wavelength sensors such as grating spectrometers, Michelson interferometers and Fabry-Perot tunable filters have been miniaturized using conventional technology, but these systems have design trade-offs among resolution, operating range, throughput, multiplexing, and complexity. We have developed a new wavelength sensing architecture that balances these parameters for applications involving imaging arrays of spectrometers. In this talk we present two different wavelength sensors based on sampling standing waves. Both sensors measure the wavelength-dependent period of optical standing waves formed by the interference of a forward and reflected wave from a mirror. The first device is a wavelength monitor, which measures the wavelength and power of a monochromatic source. The device is a GaAs NIPIN structure with two single quantum wells to sample the standing wave. The second device is a spectrometer that can also act as a selective spectral coherence sensor. The spectrometer contains two components; a large displacement piston-motion MEMS mirror and a thin GaAs photodiode flip-chip bonded to a quartz substrate. The spectrometer was demonstrated to have a resolution of 100 cm-1 (7.5 nm @ 866 nm) over an operating range of 633 nm 866 nm. The performance of this spectrometer is similar to that of a Michelson in resolution, operating range, throughput and multiplexing but with the added advantages of fewer components and one-dimensional, arrayable architecture. -------------- next part -------------- An HTML attachment was scrubbed... URL: From dwshin at stanford.edu Sun Oct 20 16:19:01 2002 From: dwshin at stanford.edu (Dong-Woon Shin) Date: Sun, 20 Oct 2002 16:19:01 -0700 (PDT) Subject: Any etchant that etches Au and Cr? Message-ID: Dear Labmembers of SNF I am currently looking for an isotropic etchant that etches Au and Cr simultaneously without attacking SiO2. (Can Al-11 aluminum etchant do that, too?) If not, I would like to know (1) whether or not cyantek CR-14 chromium etchant will attacks Au, (2) whether or not transene TFA gold etchant will attack Cr. (3) whether CR-14 and TFA will attack SiO2, Co, Fe, Ni. - The use of plastic container makes me to suspect this. Thank you. Yours truly, Dongwoon Shin FYI, CR-14 is acetic acid based etchant, TFA is potassium iodite based. From mwolfson at exajoule.com Mon Oct 21 17:06:55 2002 From: mwolfson at exajoule.com (Michael Wolfson) Date: Mon, 21 Oct 2002 17:06:55 -0700 Subject: Masks for Nikon 5:1 Stepper Message-ID: <003001c2795e$eec1a4f0$0601000a@EXAJ005> Howdy, I've got a multi-mask process and was wondering if anyone had suggestions/comments on particular maskmaking sources. In particular, has anyone had troubles with in-house laserwriter generated masks and alignment issues in the Nikon? Thanks! -- Michael Wolfson From mtang at snf.stanford.edu Mon Oct 21 13:58:19 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Mon, 21 Oct 2002 13:58:19 -0700 Subject: Special Seminar - Miniaturized Fuel Cell Systems Message-ID: <3DB46A6B.5FCFE898@snf.stanford.edu> Greetings Labmembers: One of our member companies, Lilliputian Systems, has volunteered to give a seminar on their miniaturized fuel cell technology. This seminar will be held this Wednesday, Oct. 23, at 10 am, in the CISX 101 Auditorium. Please see the abstract (appended below) for details. Please don't miss this opportunity to see what this group is up to! (And if anyone else would like to talk about their work, just let me know and we'll set something up!) Mary ____________________________________________ Miniaturized Fuel Cell Systems Sam Schaevitz, Lilliputian Systems LOCATION: Cypress Auditorium, CIS 101X TIME: Wednesday, October 23rd at 10:00 AM Abstract: Fuel cell systems which are small enough to replace batteries in today's portable electronics are under development at a number of university labs and private and public companies. This talk aims to cover the spectrum of different technologies under development, with particular attention to the practical advantages and challenges of each approach. PEM, DMFC, Alkaline, and SOFC systems will be included, as well as MEMS implementations where appropriate. Auxiliary challenges, e.g. air pumps, fuel pumps and power conditioning, will also be explored. About Lilliputian Systems, Inc.: Lilliputian Systems is a venture-backed startup which aims to produce a new power supply for portable electronics which will provide 5-10 times as much energy as Li-Ion batteries, while fitting into the same volume as the existing rechargeables. Our technology is based on efficient high-temperature MEMS devices developed at MIT, combined with thin-film Solid Oxide Fuel Cell (SOFC) technology developed at Lawrence Livermore National Labs (LLNL). We have recently been awarded a grant from the Advanced Technologies Program at NIST, and we are looking to expand our effort with qualified candidates in the areas of MEMS fabrication, SOFC design and testing, and catalyst and reformer design and testing. Interested parties should e-mail their resumes to SamS at LSInc.biz ------------------------------------------------------ Samuel B. Schaevitz Lilliputian Systems, Inc. 3-H Gill Street, Suite 200 Woburn, MA 01801 E-Mail: SamS at LSInc.biz Mobile: (617) 543-5875 -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From rcrane at snf.stanford.edu Tue Oct 22 07:57:29 2002 From: rcrane at snf.stanford.edu (Dick Crane) Date: Tue, 22 Oct 2002 07:57:29 -0700 Subject: Fire alarm testing today, 10.22.02 Message-ID: <3DB56759.BD8FFAB0@snf.stanford.edu> Just a kind reminder, There will testing of the fire sprinkler system including the outside alarm horns today, Tuesday, 11/22, from 0700 through 1430. Please disregard the outside horns during this testing period. Typically they will sound off briefly (less than 1 min.) and the horn testing will be completed in the morning. Thanks, Dick Crane From mtang at snf.stanford.edu Tue Oct 22 09:57:32 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Tue, 22 Oct 2002 09:57:32 -0700 Subject: Nano-Or Demonstration Message-ID: <3DB5837C.247AE3E2@snf.stanford.edu> Greetings Labmembers: Nano-Or Technologies manufactures an novel optical profilometry system which can be used for nanometer-scale, 3-D mapping on transparent as well as non-transparent substrates. This system is based on a conventional microscope and is said to be robust to vibration (no optical bench or special environmental controls required) and fast. Nano-Or will be setting up a system here to demonstrate its capabilities. Everyone is welcome to bring samples for analysis. A description of the system and sample guidelines is attached here. This demo is scheduled for this Thursday, Oct. 24, at 3 pm, in CIS 101 (the conference room, not the auditorium.) Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu -------------- next part -------------- A non-text attachment was scrubbed... Name: Nano-Or 250 samples guide.doc Type: application/msword Size: 152576 bytes Desc: not available URL: From Spotworthy at aol.com Tue Oct 22 18:03:07 2002 From: Spotworthy at aol.com (Spotworthy at aol.com) Date: Tue, 22 Oct 2002 21:03:07 EDT Subject: Any etchant that etches Au and Cr? Message-ID: FYI, there is a fine reference book called "Thin Film Processes" edited by John L. Vossen and Werner Kern of the Sarnoff Research Lab, put out by Academic Press, Inc. 1978 that has a ton of isotropic/anisotropic wet etch recipes. But to answer your question, basically, no. It has been my experience that there is no isotropic wet metal etchant that will attack both Au and Cr. And as Martha Stewart would say, "this is a good thing." The industry standard for many many years has been to use the KI etchant for Au, and the Cerric ammonium nitrate/acetic acid based etchants for Cr. Neither of these wet etchants will attack the SiO2. In answer to your specific questions, (1) Cyantek CR14 will not attack Au (if it did, it would be so slow that your underlying Cr would be completely undercut and your Au would lift off). (2) Transene TFA will not attack Cr (Au etch stops dead on the Cr and will undercut the photoresist mask quite rapidly, so watch your etch carefully. And if you have buried electronics in your wafer with some contacts open to the wet etch, watch out for weird electrochemical reactions that speed up the Au undercut even more). (3) Neither of these enchants will attack the SiO2. Co is pretty much only etched electrochemically. Fe will pretty much etch in nitric/hydrochloric/water based enchants and also certain electrochemical enchants. Ni will be attacked by nitric/hydrochloric/water and nitric/acetic acid/sulfuric/water combinations as well as FeCl at 43-54 C, or nitric/phosphoric/water combos. Hope this helps. Linda W. From dwshin at stanford.edu Tue Oct 22 20:08:40 2002 From: dwshin at stanford.edu (Dong-Woon Shin) Date: Tue, 22 Oct 2002 20:08:40 -0700 (PDT) Subject: Final update Au/Cr etchant In-Reply-To: Message-ID: I would like to thank Mr. Chris Kenney and Ms. Linda W. for their willingness to share their precious information with the member at SNF. Their descriptions were very precise and even more accurate than those information provided in the open sources. While I was investigating another possibility of using Cr and Cu simultaneously, I also noticed that: [For MEMS people with Cu-metallization] 1) CR14 etches Cr selectively but not Au. 2) However CR14 can etch Cu (Cu and Cr have similar chemistry.) 3) If Cu should be remaining intact during the Cr etch, CR100 can be used. Finally, I realized that MEMS-exchange website has a rough sketch of every chemicals relevant to the micro-processings. Thank you. - DWS On Tue, 22 Oct 2002 Spotworthy at aol.com wrote: > FYI, there is a fine reference book called "Thin Film Processes" edited by > John L. Vossen and Werner Kern of the Sarnoff Research Lab, put out by > Academic Press, Inc. 1978 that has a ton of isotropic/anisotropic wet etch > recipes. But to answer your question, basically, no. It has been my > experience that there is no isotropic wet metal etchant that will attack both > Au and Cr. And as Martha Stewart would say, "this is a good thing." > The industry standard for many many years has been to use the KI etchant for > Au, and the Cerric ammonium nitrate/acetic acid based etchants for Cr. > Neither of these wet etchants will attack the SiO2. > > In answer to your specific questions, > (1) Cyantek CR14 will not attack Au (if it did, it would be so slow that your > underlying Cr would be completely undercut and your Au would lift off). > (2) Transene TFA will not attack Cr (Au etch stops dead on the Cr and will > undercut the photoresist mask quite rapidly, so watch your etch carefully. > And if you have buried electronics in your wafer with some contacts open to > the wet etch, watch out for weird electrochemical reactions that speed up the > Au undercut even more). > (3) Neither of these enchants will attack the SiO2. Co is pretty much only > etched electrochemically. Fe will pretty much etch in > nitric/hydrochloric/water based enchants and also certain electrochemical > enchants. Ni will be attacked by nitric/hydrochloric/water and nitric/acetic > acid/sulfuric/water combinations as well as FeCl at 43-54 C, or > nitric/phosphoric/water combos. > > > Hope this helps. > > Linda W. > From mtang at snf.stanford.edu Wed Oct 23 08:16:01 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 23 Oct 2002 08:16:01 -0700 Subject: Seminar today! Message-ID: <3DB6BD31.3C85A36B@snf.stanford.edu> Hi all -- Just a reminder that one of our fellow labmembers, Sam Schaevitz, will be telling us all about Lilliputian Systems' work, which happens to be in one of the very coolest areas of late-breaking, applied research: micro-fuel cells. This is today (Wednesday) at 10 am, in the CISX Auditorium. Hope to see you there! Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From rcrane at snf.stanford.edu Wed Oct 23 12:28:51 2002 From: rcrane at snf.stanford.edu (Dick Crane) Date: Wed, 23 Oct 2002 12:28:51 -0700 Subject: Road work on east side of CIS building Message-ID: <3DB6F873.4208C625@snf.stanford.edu> Please see attached work announcement from John Mendoza concerning the walkway between Via Palou Mall and the Packard building on the east side of CIS building. Work will commence approximately 10/28 and go through 12/6. Except for the bike rack issue, there is minimal impact on CIS and the fab. Dick Subject: Impending building project A site improvement project on the west side of Packard EE will commence sometime next week. The work will consist of the removal of the entire asphalt walkway next to Packard extending from Serra Mall to Via Pueblo, across from the CIS building, with new pavers to be laid down in it's place. Also, new landscaping will be installed. During this time, the bike racks which are located next to the Packard Grove will in inaccessible. If you currently use these racks, please make arrangements to park elsewhere for the duration of the project, which will be approximately 6 weeks. Loud construction and construction causing large amounts of vibration (mostly demolition) will be done after hours during the week and on weekends. During construction, at times access to the Packard west entrance (CIS side) will not be available. Only pedestrian traffic will be allowed when the west entrance is open. Handicapped and wheelchair access will be limited to the entrance on the main plaza on the east side of Packard. Further information will be sent out when a confirmed start date is established. Please contact me in regards to any concerns that you may have. John Mendoza Packard Facilities Manager From mtang at snf.stanford.edu Wed Oct 23 14:53:23 2002 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 23 Oct 2002 14:53:23 -0700 Subject: Reminder: Nano-Or Demo Message-ID: <3DB71A53.AEABF6FC@snf.stanford.edu> Greetings Labmembers: Just a reminder that Nano-Or Technologies will be here to demo their optical profilometer (for nm-scale, 3-D mapping.) This will be held tomorrow (Thursday, Oct. 24), at 3 pm, in CIS 101. Everyone is invited to bring samples to test! Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From mahnaz at snf.stanford.edu Wed Oct 23 16:45:03 2002 From: mahnaz at snf.stanford.edu (Mahnaz) Date: Wed, 23 Oct 2002 16:45:03 -0700 Subject: DUV-248nm Message-ID: <3DB7347F.4C519DF7@snf.stanford.edu> Hello all, It is my pleasure to let you know that there will be a class on DUV-248 nm on Thursday 10/24/02 at 2 pm in Auditorium in CIS extension. The class will be given by Dr. Frank Yaghmaie of shipley and will cover: Short discussion of I- line resist DUV-248 nm lithography. Material aspects of polymers, photo acid generators, quenchers and what type of solvents used for 248 nm resists. Families of DUV resists, high and low activation formulations. Bi- layer lithography. use of bottom anti reflective coating. I will bring cookies Mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From thaniff at genospectra.com Thu Oct 24 14:45:06 2002 From: thaniff at genospectra.com (Tariq M. Haniff) Date: Thu, 24 Oct 2002 14:45:06 -0700 Subject: StS avail tonite 8-1030pm Message-ID: <000901c27ba6$9dd0a740$0e14a8c0@thanifflt> Sorry for the late notice, -Tariq -------------- next part -------------- An HTML attachment was scrubbed... URL: From s_harshal at yahoo.com Thu Oct 24 14:55:18 2002 From: s_harshal at yahoo.com (Harshal Surangalikar) Date: Thu, 24 Oct 2002 14:55:18 -0700 (PDT) Subject: KOH etching. Message-ID: <20021024215518.20740.qmail@web11505.mail.yahoo.com> hello labmembers, i wanted to know if anybody has worked with a common plumber's grease kind of a material to mask a Si wafer to do single side etching in KOH, as i was interested by its chemically inert and temperature resistant (180C) properties. Although i will be using a fixture to do so, i just wanted to find out if there is an easy way to mask a side and have the etching done on the other. any feedback on use of black wax would also be helpful. thank you. harshal. __________________________________________________ Yahoo! - We Remember 9-11: A tribute to the more than 3,000 lives lost http://dir.remember.yahoo.com/tribute From mcvittie at snf.stanford.edu Thu Oct 24 15:06:16 2002 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Thu, 24 Oct 2002 15:06:16 -0700 Subject: KOH etching. References: <20021024215518.20740.qmail@web11505.mail.yahoo.com> Message-ID: <3DB86ED7.212B65DD@snf.stanford.edu> Harshal, I believe black wax will hold up to KOH. Here is a note from Mike Young young at purdue.edu Purdue University ECE Dept. " We use Apiezon W, a black wax stick that softens around 100 C and dissolves in most chlorinated solvents (TCE, TCA, DCA, etc.) It can be mixed with a tiny bit of solvent to make a "goop" for applying to the sample. When allowed to dry, it behaves like a nice thick coating of resist, in terms of its resistance to wet etchants. Most US lab supply places can get it. If I recall, a place called Biddle is the "official" US distributor" Physics stores carries black wax. It has been around for ever. I used it in my 1st device processing in 1966. As for a sovent, we do not allow TCA or TCE. in the SNF lab except what is used during high temperature cleaning. I was recently told that Physics stores also carries a safe sovent. Jim McVittie It so Harshal Surangalikar wrote: > hello labmembers, > > i wanted to know if anybody has worked with a common > plumber's grease kind of a material to mask a Si wafer > to do single side etching in KOH, as i was interested > by its chemically inert and temperature resistant > (180C) properties. Although i will be using a fixture > to do so, i just wanted to find out if there is an > easy way to mask a side and have the etching done on > the other. > > any feedback on use of black wax would also be > helpful. > > thank you. > > harshal. > > __________________________________________________ > Yahoo! - We Remember > 9-11: A tribute to the more than 3,000 lives lost > http://dir.remember.yahoo.com/tribute From mr_12volt at hotmail.com Fri Oct 25 07:08:25 2002 From: mr_12volt at hotmail.com (Curtis Mead) Date: Fri, 25 Oct 2002 14:08:25 +0000 Subject: KOH etching. Message-ID: Xylenes, Toluene, and mineral spirits work as solvents. I have used Toluene and Xylenes with success. I believe Xylenes is stocked in the SNF lab. Curtis ----Original Message Follows---- From: Jim McVittie To: Harshal Surangalikar CC: labmembers at snf.stanford.edu Subject: Re: KOH etching. Date: Thu, 24 Oct 2002 15:06:16 -0700 Harshal, I believe black wax will hold up to KOH. Here is a note from Mike Young young at purdue.edu Purdue University ECE Dept. " We use Apiezon W, a black wax stick that softens around 100 C and dissolves in most chlorinated solvents (TCE, TCA, DCA, etc.) It can be mixed with a tiny bit of solvent to make a "goop" for applying to the sample. When allowed to dry, it behaves like a nice thick coating of resist, in terms of its resistance to wet etchants. Most US lab supply places can get it. If I recall, a place called Biddle is the "official" US distributor" Physics stores carries black wax. It has been around for ever. I used it in my 1st device processing in 1966. As for a sovent, we do not allow TCA or TCE. in the SNF lab except what is used during high temperature cleaning. I was recently told that Physics stores also carries a safe sovent. Jim McVittie It so Harshal Surangalikar wrote: > hello labmembers, > > i wanted to know if anybody has worked with a common > plumber's grease kind of a material to mask a Si wafer > to do single side etching in KOH, as i was interested > by its chemically inert and temperature resistant > (180C) properties. Although i will be using a fixture > to do so, i just wanted to find out if there is an > easy way to mask a side and have the etching done on > the other. > > any feedback on use of black wax would also be > helpful. > > thank you. > > harshal. > > __________________________________________________ > Yahoo! - We Remember > 9-11: A tribute to the more than 3,000 lives lost > http://dir.remember.yahoo.com/tribute _________________________________________________________________ Broadband??Dial-up? Get reliable MSN Internet Access. http://resourcecenter.msn.com/access/plans/default.asp From mwiemer at stanford.edu Tue Oct 29 13:28:57 2002 From: mwiemer at stanford.edu (Michael Wiemer) Date: Tue, 29 Oct 2002 13:28:57 -0800 Subject: High Reflection Coatings Message-ID: <001901c27f92$31d83180$6401a8c0@home> I am interested in having some high reflection (HR) coatings deposited on some of my wafers. We do not currently have the ability to stack multiple layers of dielectrics at Stanford for this purpose. I am wondering if anyone out there can recommend an outside company which could do this for us. Thank you, -Mike From Jdas at activeoptical.com Tue Oct 29 14:41:01 2002 From: Jdas at activeoptical.com (John Das) Date: Tue, 29 Oct 2002 14:41:01 -0800 Subject: Looking for dry resist process veondors Message-ID: <639B8C163707B3429AE22ACC0C3190B703FAB3@newton.activeoptical.com> Hi, We have not experienced much success trying to get an uniform resit coat/exposure process using the conventional methods on our 4 inch wafers with DRIE etched deep trenches. We are looking for a vendor who can help us with maybe some 'Riston' type dry resist coat/expose/develop process. Thank you for your help. Sincerly, John Das, AON From yy7343 at hotmail.com Wed Oct 30 16:32:49 2002 From: yy7343 at hotmail.com (Yahong Yao) Date: Wed, 30 Oct 2002 16:32:49 -0800 Subject: SIMS service in local Message-ID: Dear labmembers, Does anyone know a local company which provides SIMS service with a good price? Thanks a lot. Yahong _________________________________________________________________ Choose an Internet access plan right for you -- try MSN! http://resourcecenter.msn.com/access/plans/default.asp From guerra at par.stanford.edu Thu Oct 31 16:20:19 2002 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 31 Oct 2002 16:20:19 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 11/5/02 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Enabling High-Performance Mixed-Signal System-on-a-Chip (SoC) in High Performance Logic CMOS Technology" Luiz M Franca-Neto Intel Labs, Intel Corporation Tuesday, November 5, 2002 4:15 p.m. Building 380, Room 380X ABSTRACT We present a technique to enable the integration of sensitive analog circuits with a high performance microprocessor, on a lossy substrate that sees 190mVrms of equivalent noise at the center of the die. Measurement results of substrate noise on a Pentium 4 1GHz processor show that we can exploit the spectral content of this noise, and use appropriately tuned analog amplification to limit the isolation requirements to 70dB. By using a combination of measurement and field solver results, we show that a minimal process enhancement (i.e. a deep nwell) will yield 50 dB of isolation. We use measured mismatch data and analysis to conclude that the remaining 20dB can be achieved by symmetric matched layouts and fully differential circuit topologies. We describe two deep nwell biasing techniques (substrate noise trapping and floating deep nwell) to realize the 50dB on-die isolation. Finally, we use measurements to show that the deep nwell does not adversely impact the high frequency performance of 140nm Logic CMOS devices. BIOGRAPHY Luiz M. Franca-Neto earned his electronic degree from the ITA/CTA - Aeronautical Institute of Technology/Aerospace Technical Center, Sao Jose dos Campos, Sao Paulo, Brazil, and M.Sc. and Ph.D. degrees in Electrical Engineering from Stanford University, in 1989, 1995 and 1999, respectively. During his Ph.D. work (under Prof. James "Coach" Harris), he develop a new approach for noise phenomena in semiconductor materials, which among other developments allowed him to propose and experimentally demonstrate superior low noise microwave field effect transistor can be designed by appropriate mechanical stress and doping profile along the channel. Since 1999, he is with Intel Laboratories, where he develops advanced devices and circuits for communications and signal processing. He has 3 issued US Patents and 15 pending ones covering semiconductor devices and circuits.