EE310 Integrated Circuits Seminar, 11/5/02

Ann Guerra guerra at par.stanford.edu
Thu Oct 31 16:20:19 PST 2002


   EE310 Integrated Circuits Technology and Design Seminar

"Enabling High-Performance Mixed-Signal System-on-a-Chip (SoC)
	 in High Performance Logic CMOS Technology"

		    Luiz M Franca-Neto
	     Intel Labs, Intel Corporation

		Tuesday, November 5, 2002
			4:15 p.m.
		Building 380, Room 380X


		 	ABSTRACT

We present a technique to enable the integration of sensitive analog
circuits with a high performance microprocessor, on a  lossy substrate that
sees 190mVrms of equivalent noise at the center of the die. Measurement
results of substrate noise on a Pentium 4 1GHz processor show that we can
exploit the spectral content of this noise, and use appropriately tuned
analog amplification to limit the isolation requirements to 70dB. By using a
combination of measurement and field solver results, we show that a minimal
process enhancement (i.e. a deep nwell) will yield 50 dB of isolation. We
use measured mismatch data and analysis to conclude that the remaining 20dB
can be achieved by symmetric matched layouts and fully differential circuit
topologies. We describe two deep nwell biasing techniques (substrate noise
trapping and floating deep nwell) to realize the 50dB on-die isolation.
Finally, we use measurements to show that the deep nwell does not adversely
impact the high frequency performance of 140nm Logic CMOS devices.


			BIOGRAPHY
Luiz M. Franca-Neto earned his electronic degree from the ITA/CTA -
Aeronautical Institute of Technology/Aerospace Technical Center, Sao Jose
dos Campos, Sao Paulo, Brazil, and M.Sc. and Ph.D. degrees in Electrical
Engineering from Stanford University, in 1989, 1995 and 1999, respectively.
During his Ph.D. work (under Prof. James "Coach" Harris), he develop a new
approach for noise phenomena in semiconductor materials, which among other
developments allowed him to propose and experimentally demonstrate superior
low noise microwave field effect transistor can be designed by appropriate
mechanical stress and doping profile along the channel. Since 1999, he is
with Intel Laboratories, where he develops advanced devices and circuits for
communications and signal processing. He has 3 issued US Patents and 15
pending ones covering semiconductor devices and circuits.




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