Last Chance to Register: Internatl Workshop on Metal Gate/Work Function Science & Eng.

Jane Edwards jedwards at nishi.hostpilot.com
Sun Aug 17 15:39:54 PDT 2003


Final Announcement – Registration extended to  August 25, 2003
 
International Workshop on 
Metal Gate/Work Function Science and Engineering
 
http://www.stanford.edu/dept/chemistry/faculty/chidsey/public/Workfunction_Engineering/index.html
 
Stanford University, Stanford, CA (Braun Auditorium) 
August 28-29, 2003
 
“As we come closer to the limit of scaled CMOS, metal gate electrodes and high-K gate dielectrics are indispensable alternatives to polysilicon/silicon dioxide gates, and a broad spectrum of technical and scientific challenges are facing us. We believe this workshop will provide an exciting opportunity and forum to discuss metal gate and workfunction issues, and we strongly invite your participation.”
 
Conference Organizers:
Yoshio Nishi, Stanford University
Paul McIntyre, Stanford University
Luigi Colombo, Texas Instruments
Chris Chidsey, Stanford University
 
Agenda
 
Thursday, August 28
 
1.      Introduction and Overview, Y. Nishi
 
2.      Overview on CMOS Transistor Requirements (Gate Stack, Channel)
         a.   “Metal gate work function needs from device perspective”, Y. Taur, 
         b.   “CMOS scaling limits with high K/metal gate”, H. Iwai
         c.   “Planar CMOS and alternative structures”, D. Antoniadis
 
3.      Physics of Workfunctions                                                            
         a.   “Theory of workfunctions”, W. Harrison 
         b.   “Spectroscopic determination of workfunctions”, P. Pianetta
 
4.      Metal Gate Approaches for CMOS                                              
         a.   “High-k metal gate overview”, T. Nabatame, MIRAI project
         b.   “Dual layer metal approach”, S. Hung    
         c.   “Single layer metal approach”, T.J. King
         d.   “Metal gate CMOS integration challenges”, M. Rodder
         e.   “Metal gate electrodes”, V. Misra
 
Friday, August 29
 
5.      Metal Dielectric Interface Structure and Physics                        
         a.   “Multiscale interface modeling”, K.J. Cho
         b.   “Local electronic structure of high-k gate stacks”, J. Robertson
         c.   “Gate/dielectric interface reactions”, R. Wallace
 
6.      Mobility, High-k, SiON, Metal Gates and Strained Si (Theory and Experiment)
         a.   “Integration issues: metal gates on high mobility substrates”, S. Biesemans 
         b.   “Material aspects of high K gate integration”, S. Guha
         c.   “Ge channel MOSFETs”, C.-O. Chui      
 
7.      Electrodes and Contacts
         a.  “Schottky barrier engineering”, D. Connelly
         b.   “Channel engineering and metal gates”, K. Uchida
         c.   “Application and issues of silicides and metal integration”, K. Goto
         d.   “Metal contacts and electrodes”, (pending)
 
Panel Discussion - to be held at 7:30pm on Aug.28 after dinner at the Stanford Faculty Club
                 Moderator:  Paul McIntyre
                 Panel: Bin Yu, R. Wallace, K. Goto, D. Antoniadis, R. Gassar (tentative)
 
Registration (due August 25) is available online at
 
http://www.stanford.edu/dept/chemistry/faculty/chidsey/public/Workfunction_Engineering/index.html
 
         $300 (regular attendees – waived for invited speakers)
         $60 (students)
 


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