From rcrane at snf.stanford.edu Thu Jan 2 16:11:33 2003 From: rcrane at snf.stanford.edu (Dick Crane) Date: Thu, 02 Jan 2003 16:11:33 -0800 Subject: Fab is open for use at 5:00PM today Message-ID: <3E14D535.9ECDB013@snf.stanford.edu> Happy New Year, The fab will be open for use starting at 5:00PM today. Some equipment in the diffusion and dry etch areas needs to be qualified as to dep rates and etch rates. Please check coral or the web site for status. Most tool will be fully qualified by Monday or Tuesday. If you need an unqualified tool, please feel free to use it, but monitor your process or run a test wafer first. Please share your result as an equipment comment. Thanks. The diff and silicide wet benches will be decontaminated tomorrow morning. A few etch tools and metal dep tools are down for modifications or repairs. Check coral or the website for current status. Welcome back, Dick From aaronp at micromachine.stanford.edu Mon Jan 6 00:21:32 2003 From: aaronp at micromachine.stanford.edu (Aaron Partridge) Date: Mon, 6 Jan 2003 00:21:32 -0800 Subject: Aaron's thesis defense is this Wednesday morning at 10:00AM. Message-ID: Hello to all, I am finally defending my thesis -- come and see what I have been working on all these years. Robin is bringing food and drinks, so arrive by a bit early. Aaron. A Lateral Piezoresistive Accelerometer with Epipoly Encapsulation Aaron Partridge Wednesday January 8th, 10:00 AM CISX Auditorium This thesis presents a new accelerometer topology that combines the advantages of obliquely implanted piezoresistors on flexure sidewalls and Deep Reactive Ion Etching (DRIE) with the Bosch process to form sensitive, robust, and tightly-caged structures that detect in-plane acceleration. In addition, a new encapsulation technique is demonstrated that protects the accelerometers from mechanical and environmental damage by enclosing them under a layer of epitaxially deposited polysilicon. These design and encapsulation methods produce high performance accelerometers while allowing conventional semiconductor post processing, such as dicing, wire bonding, and other standard handling and mounting techniques. More widely, these methods can be applied to solving many long standing problems in MEMS fabrication. ----------- -------------- next part -------------- A non-text attachment was scrubbed... Name: aaron's defense poster compressed.pdf Type: application/pdf Size: 279426 bytes Desc: not available URL: -------------- next part -------------- ------------- From jac17 at stanford.edu Mon Jan 6 08:44:29 2003 From: jac17 at stanford.edu (john chiaverini) Date: Mon, 6 Jan 2003 08:44:29 -0800 (PST) Subject: etching quartz, sapphire, or alumina? Message-ID: hi, does anyone know where i can find info on etches for these materials? i have heard of HF for quartz, but nothing for sapphire or alumina. i am interested mostly in anisotropic etches, but would like to hear about any isotropic ones, as well. i am looking for an etchable low-RF-loss material... thanks a lot. john chiaverini jchiaverini at stanford.edu nobody goes there anymore, it's too crowded. --yogi berra From mcvittie at snf.stanford.edu Mon Jan 6 10:00:56 2003 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Mon, 06 Jan 2003 10:00:56 -0800 Subject: CMP Poll Message-ID: <3E19C458.D64C74D9@snf.stanford.edu> Lab Users, Novellus has offered to give us a chemical mechanical polishing (CMP) tool. They recently bought Speedfam/Ipec, which is one of the largest CMP vendors, so they have a lot of CMP experience. The present plan is to locate the CMP tool in the Ginzton Polishing Shop. To figure out the best tool for our needs, Novellus wants to know what our present and future CMP needs are. If you have present or future CMP needs, can you please reply to the following CMP poll. Note that the CMP tool will come in setup for 6 " wafers. The SNF lab is moving to 6" wafers in 2003, but we are going to try to keep a full 4" capability during a long transition period. Once we move up, the best tools will be setup for 6" wafers with 4" wafers run on the older equipment or on 6" carrier wafers with some compromises to the process results on 4" wafers. There will be more discussion on the best way to do the 6" upgrade in the months ahead. 1.Your name and group:____________________________________________________ 2.Your email address: ____________________________________________________ 3.Are you presently doing CMP: ________________________ If yes, where: ___________________________________________________________ The following questions are for present CMP users. Skip to question #9 if not present user. 4.Materials to be polished off, such as thermal oxide: __________________________________________________________________________ 5.Thickness of materials to be removed by CMP:____________________________ __________________________________________________________________________ 6.Line-widths of features to be polished down: ___________________________ 7.Percent of wafer area to be polished down: ___________________________ 8.Wafer Size: _____________ 9.How difficult will it be for you to transition to 6" wafers: _________ (Use #) 1- easy to 5 - extremely difficult or "Im" for impossible (such as with GaAs wafers) 10.Typical lot size: _________ # of wafers The follow questions are for future CMP needs: 11.When do you expect to have a CMP need: _________ year, ________ quarter 12.Materials to be polished off, such as thermal oxide: ___________________ ___________________________________________________________________________ 13.Thickness of materials to be removed by CMP:____________________________ ___________________________________________________________________________ 14.Line-widths of features to be polished down: ____________________________ 15.Percent of wafer area to be polished down:_____________________________ 16.Wafer Size: _____________ 17.How difficult will it be for you to transition to 6" wafers: _________ (Use #) 1- easy to 5 - extremely difficult or "Im" for impossible (such as working with GaAs wafers) 18.Typical lot size: _________ # of wafers Thanks, Jim McVittie Please return this poll to Jim McVittie (mcvittie at snf.stanford.edu/ Rm 336 CISX/ on to my mailbox in the CIS receiving area. -------------------------------------------------------------- James P. McVittie Senior Research Scientist Allen Center for Integrated Systems jmcvittie at stanford.edu Stanford University Tel: (650) 725-3640 Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 -------------- next part -------------- A non-text attachment was scrubbed... Name: CMP-Poll.doc Type: application/msword Size: 49152 bytes Desc: not available URL: From aaronp at micromachine.stanford.edu Tue Jan 7 08:49:56 2003 From: aaronp at micromachine.stanford.edu (Aaron Partridge) Date: Tue, 7 Jan 2003 08:49:56 -0800 Subject: Thesis defense time moved up one hour to 9:00 AM Message-ID: <0D390CEE-2260-11D7-8F73-00039357B66C@micromachine.stanford.edu> All, My thesis defense has been moved up one hour from 10:00 AM to 9:00 AM on Wednesday January 8th (tomorrow!). It will be held in the CISX Auditorium. Come early and enjoy some Pete's coffee. Aaron Partridge ---------- -------------- next part -------------- A non-text attachment was scrubbed... Name: defense poster compressed.pdf Type: application/pdf Size: 288937 bytes Desc: not available URL: -------------- next part -------------- ---------- From jerabek at snf.stanford.edu Tue Jan 7 09:28:36 2003 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Tue, 7 Jan 2003 09:28:36 -0800 (PST) Subject: LRS-18 maskwriter Message-ID: Status of mask writer is as follows: as you may remember just before Christmas shutdown the writer developed a problem of spurious exposures on a return stroke of the stage.The problem is still there.Micronic field service after extensive search decided the problem is with a laser beam shutter. Unfortunately this item has to be shipped from Sweden (yes it is a Swedish machine). It should arive here Thursday morning and field service will install it that day. I will know by then if that is a fix and let you know. -Paul From shott at snf.stanford.edu Wed Jan 8 09:53:03 2003 From: shott at snf.stanford.edu (John Shott) Date: Wed, 08 Jan 2003 09:53:03 -0800 Subject: Parking in the rear lot ... Message-ID: <3E1C657F.E0F3DF3E@snf.stanford.edu> SNF Labmembers and CIS Building residents: Let me remind you that parking in the loading dock area is for vendors, contractors, and deliveries. It should not be used for general visitors or for our own use if we are unable to find a space elsewhere. There are a variety of alternative options for one day parking for general visitors to the building. Deliveries come at all hours of the day and delivery of liquid nitrogen and other cryogenic gases can occur at any time. Additionally, contractors and vendors often have heavy equipment that necessitates close proximity to the building. Occasionally, there are cases where each of us may be picking up or dropping off equipment. Tony Souza will be happy to accommodate those needs ... but, as soon as the equipment is loaded/unloaded, we should move our vehicles out of the loading dock area to a normal parking area. Thank you for your support ... we are all dependent on reliable and timely delivery of supplies to this building and need to insure that we have adequate space for that to occur. John From mtang at snf.stanford.edu Thu Jan 9 08:57:43 2003 From: mtang at snf.stanford.edu (Mary Tang) Date: Thu, 09 Jan 2003 08:57:43 -0800 Subject: EE410 is in the lab! Message-ID: <3E1DAA07.C0506698@snf.stanford.edu> Greeting Labmembers: I just wanted to let you all know that SNF's favorite Winter term class, EE410, is now commencing. There will be 18 students (spread across 3-4 lab sections) working in the lab over the next six weeks. They will be fabricating a complete CMOS device, so this is an aggressive schedule. There will also be a lot of behind-the-scenes work done by the lab TA's. So, please be aware that there will be hands-on classes taking place in the lab at various tools (students will be supervised at all times by TA's). And please understand that the TA's will have priority on some tools, as they need to keep to the aggressive processing schedule. We are extremely fortunate to have a remarkably good group of lab experts (and familiar faces!) on hand who will no doubt make every effort to process efficiently and minimize possible general lab disruptions. If you have any questions, please contact them. Gladys Sarmiento (gladys at snf) will be coordinating activities in the lab. The course TA's are Sameer Jain (sjain), Hemanth Jagannathan (jhemanth), Kailash Gopalakrishnan (kailash), and Ammar Nayfeh (anayfeh). (By the way, for those of who are unfamiliar with EE410 and interested in device processing, you might want to find out more from the TA's. The process has been developed and honed over ten of more years and although is fully CMOS, has a lot of truly creative methods of exploiting processing tricks to minimize fabrication time.) Thanks for your attention and consideration -- Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at snf.stanford.edu From jerabek at snf.stanford.edu Fri Jan 10 08:50:12 2003 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Fri, 10 Jan 2003 08:50:12 -0800 (PST) Subject: LRS-18 mask writer Message-ID: O.K. a good news is the spurious exposures on the return stroke are gone (beam shutter was O.K. , it just needed realignment). I have written two very long exposures of contact masks, which run without problem. Then I started to write EE410 Ultratech reticle and got numerous "delivery card" errors and the job eventualy crashed and reported at the end "unstable laser power". I left the sustem alone for about 1 hr. and then succesfuly written another two contact masks. Right now I am in process of test writing EE410 reticle to determine if the yesterday event was one of the kind (caused possibly by a power glitch) or a specific to the EE410 files. -Paul From lgx at stanford.edu Fri Jan 10 15:13:49 2003 From: lgx at stanford.edu (Guanxiong Li) Date: Fri, 10 Jan 2003 15:13:49 -0800 Subject: wire bonding service Message-ID: <052501c2b8fd$eee559c0$976a40ab@stanford.edu> Hi, Does anyone know any wire-bonding services on- or off-campus which I can use? If yes, would you please provide me the contact info? Thanks a lot! Regards, Guanxiong Li ----------------------------------------- Materials Science and Engineering Stanford University McCullough 208 Phone: 650-723-2939 ------------------------------------------ -------------- next part -------------- An HTML attachment was scrubbed... URL: From tomchang65 at yahoo.com Fri Jan 10 16:56:56 2003 From: tomchang65 at yahoo.com (Tom H. Chang) Date: Fri, 10 Jan 2003 16:56:56 -0800 (PST) Subject: Polymer Process Shop In-Reply-To: <052501c2b8fd$eee559c0$976a40ab@stanford.edu> Message-ID: <20030111005656.34971.qmail@web20706.mail.yahoo.com> Hi: Does anyone knows local resources to process polymer, like hot embossing or injection molding? I appreciate the info. Tom Chang Tom Chang 650-967-3812 650-814-3888(Cell) Tomchang65 at yahoo.com -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Mon Jan 13 15:14:58 2003 From: guerra at par.stanford.edu (Ann Guerra) Date: Mon, 13 Jan 2003 15:14:58 -0800 (PST) Subject: SPECIAL SEMINARS: ISSCC03 presentations Message-ID: SPECIAL SEMINAR Two of the 2003 ISSCC (IEEE International Solid-State Circuits Conference) presentations will be given on Tuesday, February 4, 2003 10:00 a.m. CIS-101 Linvill Room "A 20-GS/s 8-bit ADC with a 1-MB Memory in 0.18-um CMOS" given by Brian Setterberg Agilent Labs A 20GS/s 8-bit ADC achieves a bandwidth of 6GHz in 0.18um CMOS. The implementation uses 80 time-interleaved current-mode pipeline sub-ADCs and stores data at 20GB/s into a 1MB on-chip memory. The ADC is packaged with a BiCMOS input buffer chip in a 438-ball BGA, and total power consumption is 10W. "A 12b 75MS/s Pipelined ADC using Open-Loop Residue Amplification" B. Murmann, B. E. Boser University of California, Berkeley, CA The multi-bit first stage of a 12b 75MS/s pipelined ADC uses an open-loop gain stage to achieve more than 60% residue amplifier power savings over a conventional implementation. Statistical background calibration removes linear and nonlinear residue errors in the digital domain. The prototype IC achieves 68.2dB SNR, -76dB THD, occupies 7.9mm^2 in 0.35m CMOS and consumes 290mW at 3V. From Jane.Edwards at stanford.edu Wed Jan 15 18:00:15 2003 From: Jane.Edwards at stanford.edu (Jane Edwards) Date: Wed, 15 Jan 2003 18:00:15 -0800 Subject: Request from Prof. Nishi re: SNF Project Summary Message-ID: A Happy New Year to you all. The year 2003 will be another challenging year for the SNF. Our current contract with NSF will expire in December and we are busy preparing for the re-competition for the NNIN (National Nanotechnology Infrastructure Network) which will be the new name of the university network for nanotechnology. As part of our current reporting requirements to the NSF we have been asked to obtain research summaries from our lab users. These summaries will be published in a booklet and distributed by NSF and NNUN. Your help in sending us a summary of your work at the SNF during October 2001 to the present would be greatly appreciated. Ideally, the summaries would consist of either a 250 word report/abstract with 2 figures or a 100 word report/abstract with 1 figure. However, we will accept any of the following: 1. Reprint of published work done at SNF 2. Copy of conference poster or talk 3. Any conference abstract (accepted or not) This summary will take the place of the slides that we have requested of labmembers in previous years. Since these summaries will be made available to a forum outside of SNF, please do not include any proprietary information or results that have not yet been formally presented or published. Please send your summary to Jane Edwards (jane.edwards at stanford.edu) by Friday, January 24. Include the report header information Report Title: Author(s): Principal Investigator: Dept, Institution, State Thanks once again for your continued support. Yoshio Nishi Director, Stanford Nanofabrication Facility Professor of Electrical Engineering (Research) Stanford University nishiy at stanford.edu From rjchen at stanford.edu Wed Jan 15 18:35:58 2003 From: rjchen at stanford.edu (Robert J. Chen) Date: Wed, 15 Jan 2003 18:35:58 -0800 (PST) Subject: fused silica wafers? Message-ID: Hi all, Was wondering if anyone knows where I might be able to find a source for fused silica wafers (as opposed to quartz or glass)? Thanks, -Robert Chen From EricS at Bridgewave.com Wed Jan 15 20:37:51 2003 From: EricS at Bridgewave.com (Eric Sanjuan) Date: Wed, 15 Jan 2003 20:37:51 -0800 Subject: Insoluble Cu compound? Message-ID: hi all, Does anyone know what is the black compound, that is produced on the copper surface, when etching gold with KI/I2 in the presence of copper? (possibly CuI2?) If so, do you know how to remove it. Either home brewed mixtures and/or chemical vendor products will do. thx and have a good day. Eric S. From gray at ee.Stanford.EDU Thu Jan 16 10:34:14 2003 From: gray at ee.Stanford.EDU (Robert M. Gray) Date: Thu, 16 Jan 2003 10:34:14 -0800 Subject: Special EE Seminar Message-ID: <200301161834.h0GIYEI02853@ee.Stanford.EDU> EE Special Seminar Noon Friday 24 January 2003 Packard EE 202 Suprathreshold Visual Psychophysics and Applications to Image Compression Sheila S. Hemami School of Electrical & Computer Engineering, Cornell University http://foulard.ece.cornell.edu Image compression has reached the peak of efficiency in terms of treating images as traditional "signals," employing efficient transformations, correlation-based models, and context-based coding. Human visual system characteristics have been successfully applied to high-rate signal-based compression, where stimuli such as compression-induced distortions are below the visibility threshold; these distortions and this compression regime are called subthreshold. Operation of such signal-based compression algorithms in the suprathreshold regime (i.e., low-rate compression), in which compression-induced distortions are clearly visible, has to date operated based on visual system rules-of-thumb and has produced moderate success. However, a unifying approach to produce higher-quality low-rate images is lacking. In this talk I will describe our work toward a robust, unified approach to psychovisually motivated low-rate image compression. Experimentation and results have produced a robust distortion allocation strategy based on RMS contrast which is applicable to wavelet-based compression and can be used successfully over the entire range of compression ratios. Sheila S. Hemami received her PhD in EE at Stanford University in 1994. She is currently an Associate Professor of Electrical Engineering and Director of the Visual Communications Lab at Cornell University. From afflannery at attbi.com Thu Jan 16 12:05:52 2003 From: afflannery at attbi.com (Anthony Flannery) Date: Thu, 16 Jan 2003 12:05:52 -0800 Subject: Insoluble Cu compound? References: Message-ID: <001601c2bd9a$ac90a8d0$4201a8c0@transparentnetworks.com> Eric, One thing you can try is ammonium persulfate. It is used to etch copper. It should not etch the gold. It may attack Ti but at a slower rate than the Cu. We do a short etch with it that does not undercut Ti adhesion layers. It will probably eat into an organic substrate (polyimide, photoresist) as it is a strong oxidizer. You can buy it at Frye's (I think). Sodium Persulfate is also used. Check out http://www.mgchemicals.com/products/410.html Tony Flannery ----- Original Message ----- From: "Eric Sanjuan" To: Sent: Wednesday, January 15, 2003 8:37 PM Subject: Insoluble Cu compound? hi all, Does anyone know what is the black compound, that is produced on the copper surface, when etching gold with KI/I2 in the presence of copper? (possibly CuI2?) If so, do you know how to remove it. Either home brewed mixtures and/or chemical vendor products will do. thx and have a good day. Eric S. From shott at snf.stanford.edu Thu Jan 16 11:01:21 2003 From: shott at snf.stanford.edu (John Shott) Date: Thu, 16 Jan 2003 11:01:21 -0800 Subject: Coral is dead!!! Message-ID: <3E270181.79B5F102@snf.stanford.edu> SNF Lab Members: As many of you already know, Coral died this morning at 8 a.m. At this point, we are still determining whether it is a disk failure or a database problem ... but, at the moment, it appears that Coral will be down for at least several more hours. Accordingly, we've manually "green lighted" all equipment that has hardware interlocks and then asked the staff to place signs that say "SHUTDOWN" on any piece of equipment that should not be used. You are welcome to use the lab, but I would ask you to do the following: 1. Keep notes of which pieces of equipment you use and for how long so that we may capture this information after the fact. 2. Please respect the "SHUTDOWN" signs and ask appropriate staff members as to the operational status of each piece of equipment. We don't want a Coral outage to result in damage to laboratory equipment. 3. Communicate amongst yourselves to try to determine who had equipment reserved and who is going to use equipment next ... particularly for the heavily used pieces of equipment. 4. Naturally, please don't use equipment for which you are not yet qualified. I apologize for this Coral outage. We are doing our best to determine the nature of our problem and to get it repaired as quickly as possible. I will keep you apprised of further developments. Thank you for your support ... particularly during this Coral outage. John From rjchen at stanford.edu Thu Jan 16 17:32:53 2003 From: rjchen at stanford.edu (Robert J. Chen) Date: Thu, 16 Jan 2003 17:32:53 -0800 (PST) Subject: fused silica wafers? In-Reply-To: <3E261C5D.77CB16D@snf.stanford.edu> Message-ID: Thanks for all the suggestions, I got some good leads to check up on... -Robert From bmurray at snf.stanford.edu Fri Jan 17 05:22:17 2003 From: bmurray at snf.stanford.edu (Bill Murray) Date: Fri, 17 Jan 2003 05:22:17 -0800 (PST) Subject: Coral is up and running! Message-ID: Labmembers, We had a failure of one of the disk drives on our database server. As a result, we had significant corruption of the database. We have resolved the hardware problem and restored the database. Coral is now up and running. Please enable any equipment that you are currently using. We did test the restored database. However, if you notice any problems, let us know right away. Thanks for your patience, Team Coral From ddisney at powerint.com Fri Jan 17 09:20:06 2003 From: ddisney at powerint.com (Donald Disney) Date: Fri, 17 Jan 2003 09:20:06 -0800 Subject: Availability of MeV ion implant service? Message-ID: Labmembers, I am looking for someone to provide very high energy (> 1MeV) ion implantation services. If any of you have any leads, please send them to me. Thanks! Don Disney From shott at snf.stanford.edu Fri Jan 17 10:34:09 2003 From: shott at snf.stanford.edu (John Shott) Date: Fri, 17 Jan 2003 10:34:09 -0800 Subject: Recovery from Coral database/hardware problems ... Message-ID: <3E284CA1.C75ACD8D@snf.stanford.edu> SNF Lab Members: As you have seen from Bill and Mike's previous message ... Coral came back on line at about 5:15 this morning. We believe that we lost virtually no data ... other than, of course, the data that we failed to capture yesterday during the "all on" equipment conditions. As the final step in this recovery, I need your help with two things: First, for pieces of equipment that are hardware interlocked, there is likely a significant inconsistency between what Coral thinks is enabled and what the hardware interlock thinks is enabled since we were running the hardware interlocks "all on" yesterday. While I can enforce this myself, it would be better if each of you would check this consistency yourself ... it will reduce the chance that I accidentally disable something that you are actually using. So, if you notice that the "ON" light is on (meaning that the hardware interlock thinks that equipment is enabled) but Coral doesn't think it is enabled ... how can you fix this? 1. If you enable the equipment the Coral will now think that it is enabled and it will send an "enable" pulse to the hardware interlock ... to they will both be consistent and enabled. 2. Then, if you don't want to actually use the equipment, disable it immediately. This will make sure that it is disabled in both Coral and the hardware interlock system. The second thing that I would like your help in: if you used equipment yesterday, would you please send me e-mail indicating which equipment you used and the start/stop times of that usage so that I can manually an equipment activity record into the database for you? If you work on more than one project/account, please tell me which should be used for this particular activity. This will both allow us to have better records of actual equipment usage, but will also allow us to properly charge people for their equipment usage. Finally, we do have plans to replace the aging (and apparently failing) Coral server/database machine with newer hardware including RAID disks to minimize the likelihood of a repeat hardware failure of this type. We believe that that hardware should be avialable and in use in approximately two weeks. Once again, we apologize for the inconvenience created by this unplanned Coral outage and are taking steps to reduce the likelihood of similar future events. Thank you for your continued support, John p.s. Recovering the data as completely as we did on a corrupted database running on top of failed/failing disk hardware is not an easy task. Bill Murray and Mike Bell each should be thanked for their skill and persistence in resolving this issue in a timely fashion. From mahnaz at snf.stanford.edu Wed Jan 22 11:15:37 2003 From: mahnaz at snf.stanford.edu (Mahnaz) Date: Wed, 22 Jan 2003 11:15:37 -0800 Subject: Seminar Message-ID: <3E2EEDD9.AFBF5F39@snf.stanford.edu> Hello all, Sorry about the error the date is I am very pleased to announce that there will be a seminar on silicon to silicon bonding given by Dr. Shari Farrens of EV group. Dr. Farrens is the chief scientist at EVG and very well known in the world of si to si bonding. She is willing to answer all other questions regarding anodic bonding as well. Please mark your calendar for Thursday 2/6/03 2 pm CIS Auditorium. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From jedwards at nishi.hostpilot.com Wed Jan 22 12:54:15 2003 From: jedwards at nishi.hostpilot.com (Jane Edwards) Date: Wed, 22 Jan 2003 12:54:15 -0800 Subject: REMINDER: Request for SNF Project Summary Message-ID: Hi, This is just a quick reminder that we are still gathering project summaries (see email below for details). Your help is desperately needed. Please send in a summary by Friday, Jan. 24. Thanks for all your help. -Jane Edwards jane.edwards at stanford.edu -----Original Message----- From: Jane Edwards [mailto:Jane.Edwards at stanford.edu] Sent: Wednesday, January 15, 2003 6:00 PM To: 'labmembers at snf.stanford.edu' Cc: 'Edwards'; 'Janine Hannibal' Subject: Request from Prof. Nishi re: SNF Project Summary A Happy New Year to you all. The year 2003 will be another challenging year for the SNF. Our current contract with NSF will expire in December and we are busy preparing for the re-competition for the NNIN (National Nanotechnology Infrastructure Network) which will be the new name of the university network for nanotechnology. As part of our current reporting requirements to the NSF we have been asked to obtain research summaries from our lab users. These summaries will be published in a booklet and distributed by NSF and NNUN. Your help in sending us a summary of your work at the SNF during October 2001 to the present would be greatly appreciated. Ideally, the summaries would consist of either a 250 word report/abstract with 2 figures or a 100 word report/abstract with 1 figure. However, we will accept any of the following: 1. Reprint of published work done at SNF 2. Copy of conference poster or talk 3. Any conference abstract (accepted or not) This summary will take the place of the slides that we have requested of labmembers in previous years. Since these summaries will be made available to a forum outside of SNF, please do not include any proprietary information or results that have not yet been formally presented or published. Please send your summary to Jane Edwards (jane.edwards at stanford.edu) by Friday, January 24. Include the report header information Report Title: Author(s): Principal Investigator: Dept, Institution, State Thanks once again for your continued support. Yoshio Nishi Director, Stanford Nanofabrication Facility Professor of Electrical Engineering (Research) Stanford University nishiy at stanford.edu From ericp at snf.stanford.edu Thu Jan 23 04:55:19 2003 From: ericp at snf.stanford.edu (Eric Perozziello) Date: Thu, 23 Jan 2003 04:55:19 -0800 (PST) Subject: Deep Silicon Etch talk by Alcatel Wednesday morning Message-ID: Dear Labusers, If you like to etch deep into silicon, you should be at this talk. Please come! _______________________________________________________________ Deep Silicon Etch Presentation Robert Fucci and Jean-Marc Thevenoud Alcatel Vacuum Products Wednesday, January 29, 2003 10:00 AM CISX Auditorium Alcatel Vacuum Products has been active in the deep silicon etch process for years. This includes both the "Bosch" gas-switched process and the cryogenic non-switched process. Recent devolpments in deep silicon etching will be presented. Work in conjunction with Bosch Corporation has yielded many improvements, including a doubling of etch rates. Alcatel has also improved many other aspects of the process including elimination of the aspect-ratio dependence (that is, smaller features generally etch slower than larger features) under certain conditions. Other areas of improvement include fast gas switching for smoother sidewalls, and active pressure control for each cycle during processing. Many lab users are familiar with our current deep silicon etcher, the STSetch tool. Given the popularity of this process in the lab, there is significant interest in obtaining a newer-generation tool, capable of higher throughput (up to 20 micron per minute) and more advanced process capability. More information on the equipment can be found at: http://www.alcatelvacuum.com/alcatel_avt/download/docs/prod/doc2prod38.pdf From cshen at briontech.com Thu Jan 23 10:02:34 2003 From: cshen at briontech.com (cshen at briontech.com) Date: Thu, 23 Jan 2003 10:02:34 -0800 (PST) Subject: silver paste In-Reply-To: References: Message-ID: <63930.171.64.100.112.1043344954.squirrel@mail.briontech.com> Dear labmembers, Does anyone have silver paste, or other conductive paste? Can I borrow a little bit?Thanks a lot for your help. Chongfei From rcrane at snf.stanford.edu Thu Jan 23 16:26:47 2003 From: rcrane at snf.stanford.edu (Dick Crane) Date: Thu, 23 Jan 2003 16:26:47 -0800 Subject: HEPA fan maintenance Saturday in litho Message-ID: <3E308847.B97A044@snf.stanford.edu> Dear litho users, Facilities will be replacing two fan motor drive controllers in the litho area on Saturday, January 25, from 0700 through 1700. The controllers will be replaced one at a time. The ceiling HEPA air filters will not have air flow during the work. While half of the litho area will have air flow at any given time, there will be an increase in particle count in the non-flow area. So if your process is particle sensitive, please avoid using litho on Saturday. Sorry for the inconvenience, Dick From cshen at briontech.com Mon Jan 27 21:30:19 2003 From: cshen at briontech.com (Chongfei Shen) Date: Mon, 27 Jan 2003 21:30:19 -0800 Subject: W etch Message-ID: Dear labmembers, Does anyone know how to dry etch W without etching Cr? Chongfei From SamS at LSInc.biz Thu Jan 30 12:02:27 2003 From: SamS at LSInc.biz (Samuel B. Schaevitz) Date: Thu, 30 Jan 2003 12:02:27 -0800 Subject: Alumina etch rate in HF? Message-ID: <5.1.0.14.2.20030130120046.038be008@pop.lilliputiansystemsinc.com> Hey All, Does anyone know the approximate etch rate of alumina (aluminum oxide) in an HF solution (e.g. BOE, 49%HF, 50:1HF, etc)? Any info would be useful. Thanks, Sam ------------------------------------------------------ Samuel B. Schaevitz Lilliputian Systems, Inc. 3-H Gill Street, Suite 200 Woburn, MA 01801 E-Mail: SamS at LSInc.biz Mobile: (617) 543-5875 From mahnaz at snf.stanford.edu Thu Jan 30 12:12:04 2003 From: mahnaz at snf.stanford.edu (Mahnaz) Date: Thu, 30 Jan 2003 12:12:04 -0800 Subject: Blanket mask Message-ID: <3E398714.4E7C9A04@snf.stanford.edu> Hello all, Please bring my blanket masks ( both) back as soon as possible. I have a user that needs it and has been waiting since yesterday. This is not nice, you can purchase your own from Paul. mahnaz From nmehenti at stanford.edu Fri Jan 31 17:03:18 2003 From: nmehenti at stanford.edu (Neville Mehenti) Date: Fri, 31 Jan 2003 17:03:18 -0800 Subject: ITO processing Message-ID: <5.1.0.14.2.20030131170109.02a66b88@nmehenti.pobox.stanford.edu> Hello, I was wondering if someone familiar with ITO processing would have a few minutes to discuss some questions I have about etching ITO and depositing metals on top. If so, I would greatly appreciate it. Of course, I can meet at your convenience. Any feedback would be great. Thanks for your time, Neville Mehenti mehenti at snf.stanford.edu