Brian Greene - Ph.D. Dissertation Defense, Wednesday 9AM

Brian Greene BGreene at stanford.edu
Mon Mar 24 10:40:44 PST 2003


Department of Applied Physics - University Ph.D. Dissertation Defense

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Lateral Solid Phase Epitaxy of Silicon and Application to the Fabrication of
MOSFETs

 

Brian J. Greene

Advisors: Prof. J. F. Gibbons and Prof. J. L. Hoyt

 

9:00 AM

Wednesday, March 26, 2003

Center for Integrated Systems Extension Auditorium (CIS-101X)

Refreshments at 8:45 AM

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Thin film silicon on insulator fabrication is an increasingly important
technology requirement for improving performance in future generation
devices and circuits.  One process for SOI fabrication that has recently
been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of
silicon over oxide. This process involves annealing amorphous silicon that
has been deposited on oxide patterned Si wafers.  The (001) Si substrate
forms the crystalline seed for epitaxial growth, permitting the generation
of Si films that are both single crystal, and oriented to the substrate.
This method is particularly attractive to fabrication that requires low
temperature processing, because the Si films are deposited in the amorphous
phase at temperatures near 525°C, and crystallized at temperatures near 570
°C.  It is also attractive for applications requiring three dimensional
stacking of active silicon device layers, due to the relatively low
temperatures involved.

 

For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order
of 10 nm

will be required.  One limitation of the LSPE process has been the need for
thick films (0.5 - 2 μm) and/or heavy P doping (1019 - 1020 cm-3) to
increase the maximum achievable lateral growth distance, and therefore
minimize the area on the substrate occupied by seed holes.  This talk will
discuss the characterization and optimization of process conditions for
large area LSPE silicon film growth, as well as efforts to adapt the
traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25
nm) while avoiding the use of heavy active doping layers.  MOSFETs
fabricated in these films that exhibit electron mobility comparable to the
Universal Si MOS Mobility will be described. 

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