From katsuo at umich.edu Wed Oct 1 10:01:47 2003 From: katsuo at umich.edu (Katsuo Kurabayashi) Date: Wed, 01 Oct 2003 13:01:47 -0400 Subject: ZnO Deposition In-Reply-To: <3F560B34.CA2812B5@snf.stanford.edu> Message-ID: <5.2.1.1.2.20031001125754.02436740@srvr5.engin.umich.edu> Does anyone know where you can deposit a ZnO layer on a silicon wafer using sputtering? Is the microfab lab in Ginzton still available for that? If you know any information on it, please let me know. Thank you, ************************************************************* Katsuo Kurabayashi, Ph.D. Assistant Professor Mechanical Engineering & Macromolecular Science and Engineering University of Michigan Room 2272 G.G. Brown Lab Ann Arbor, MI 48109-2125 Tel: (734) 615-5211 Fax: (734) 647-3170 e-mail: katsuo at umich.edu Web: http://www-personal.umich.edu/~katsuo *************************************************************** -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Wed Oct 1 13:40:37 2003 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 1 Oct 2003 13:40:37 -0700 (PDT) Subject: EE310 Integrated Circuits Seminar, 10/7/03 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Resistor-Capacitor Circuits for Fun and Profit" Mark Johnson Matrix Semiconductor Tuesday, October 7, 2003 4:15 p.m. Building 380, Room 380X ABSTRACT The goals of this work are: (1) to have fun, and (2) to possibly make some money. We'll discuss some very simple electronic filter circuits, realized with resistors, capacitors, and opamps. These filters are fed an input "signal" which is the price data stream of a traded security such as a stock, bond, stock option, commodity, etc. The outputs from these filters are unambiguous binary digital signals "BUY" and "SELL". Perhaps surprisingly, these circuits made from 99 cents' worth of Radio Shack parts perform agreeably well when tested on 20 years of actual market data. In simulated trading the profits exceed 40% / year, compounded, even after including the effects of commissions and adverse trade executions ("slippage"). These concepts have also been implemented and tested in real- world trading, executing real trades on real exchanges using real money, for the past seven years (12/31/96 to 9/25/2003). Performance results collected in the seven year real-money test will be presented. ----------------------------------------------------------- Biography of speaker: Mark Johnson received a BSEE from Rice University in 1979, and an S.M. from MIT in 1982. His career as a circuit designer has alternated between memory chips and micro- processors. He began at Mostek where he designed 16 Kbit SRAMs, 64K and 1Megabit DRAMs. Then he moved to MIPS Computer Systems, where he helped design 3 generations of CMOS CPUs and an ECL CPU. Returning to DRAMs, he joined Rambus where he helped develop the 4MBit and 16Mbit generations of R-DRAM circuits. Then he joined Transmeta, where he designed RAMDAC, PLL, and low voltage I/O circuits aboard the Crusoe CPU. In 1988 he co-founded Matrix Semiconductor, where he holds the position of Chief Circuit Technologist. Mr. Johnson is a member of Sigma Xi, has received the ISSCC Best Paper Award twice, and has been awarded 28 U.S. Patents. From mtang at snf.stanford.edu Thu Oct 2 11:10:15 2003 From: mtang at snf.stanford.edu (Mary Tang) Date: Thu, 02 Oct 2003 11:10:15 -0700 Subject: New Staff Member Message-ID: <3F7C6A07.9BB3632B@snf.stanford.edu> Greetings Labmembers! Please join me in welcoming Colby Bellew to our SNF staff! He is working in the litho area as process engineer, focusing initially on wafer bonding and the AFM, as well as helping Mahnaz out with general litho support. Many of you already know Colby (if not his adorable little one, Claire) -- he's a former industrial labmember here and previous to that, spent loads of time doing graduate work in the Berkeley Microlab. So, Colby is extremely experienced and knowledgeable. He's been "one of us" (in the SNF labmember community) for a couple of years now, but now has come over to join the us staffers on the dark side... Stop by CIS 143 or in the litho area to say "hi" -- again... Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From sandrew at stanford.edu Fri Oct 3 14:37:26 2003 From: sandrew at stanford.edu (Scott D. Andrews) Date: Fri, 3 Oct 2003 14:37:26 -0700 (PDT) Subject: Problems with PMMA as a mask Message-ID: Has anyone tried using PMMA as a mask when etching SiO2? I need to etch 10 nm of SiO2 with 100 nm of PMMA as the mask layer. However, when I use the mrc with O2 and freon 23, the PMMA does not survive. Ideally, I would like an anisotropic etch, but if necessary, I would accept a wet process that undercuts slightly. Thanks, Scott Andrews From shott at snf.stanford.edu Mon Oct 6 07:37:23 2003 From: shott at snf.stanford.edu (John Shott) Date: Mon, 06 Oct 2003 07:37:23 -0700 Subject: New project and account names .... Message-ID: <3F817E23.1090501@snf.stanford.edu> SNF Lab Members: This morning we converted the Coral database to use new project names and account numbers. While we have tested this conversion extensively in hopes of inconveniencing as few of you as possible, there may be a handful of you who either cannot start Coral or who still see your old style project and account names. If this happens to you, please send e-mail to coral at snf.stanford.edu and we will work to fix this problem as quickly as possible. To make sure that you are not affected at a critical time, you may want to fire up Coral to test things out in advance of really needing it. The easiest way to test this out is to begin to make a reservation ... The popup window includes a pulldown window labelled "Project:". This should now include your company name, if you are an industrial user, and a name tht looks like "faculty_name (Project Name)" if you are a Stanford student, and a name that looks like "University_name (faculty)" if you are a non-Stanford student. If you select each of your projects, you should see an account number that looks like: 1234567-123-ABCDE .... 7-digits, a hyphen, from 1 to 8 more digits, another hyphen, and 5 capital letters. If you see the old style 2DPG400, 9VAV789 project or account number, something needs to be fixed in your records. If you see any of these, please let us know ... we need to address this quickly because the old style numbers are no longer valid and will ALL be turned off in a day or two. Thank you for your support, John From jwc at snf.stanford.edu Fri Oct 3 18:17:11 2003 From: jwc at snf.stanford.edu (James Conway) Date: Fri, 03 Oct 2003 18:17:11 -0700 Subject: Problems with PMMA as a mask -- Try this! References: Message-ID: <3F7E1F97.8957E711@snf.stanford.edu> Hello: Two things that will help you: 1- NO Oxygen during the etch process, and be sure to pump the system to base pressure before back filling and flowing your process gases for several minutes. PMMA and most of the ebeam resist materials (ZEP-520 for example) will quickly be removed with even the slightest trace of Oxygen in the process gases. My old descum process was 15 W 30 sec. 0.200 mT O2 in a March Mini-80 RIE system. This will rapidly decompose the ZEP-520 material. 2. Post develop bake on hot plate or preferably in N2 oven for 10 - 30 minutes. I recommend 90 - 110 degrees C. This will assist cure and cross linking of the resist material making it more resistant to the RIE process. Please reply with your notes and results when you have tried this to add to our knowledge base. Thanks, James Conway "Scott D. Andrews" wrote: > Has anyone tried using PMMA as a mask when etching SiO2? I need to etch > 10 nm of SiO2 with 100 nm of PMMA as the mask layer. However, when I use > the mrc with O2 and freon 23, the PMMA does not survive. Ideally, I would > like an anisotropic etch, but if necessary, I would accept a wet process > that undercuts slightly. > > Thanks, > Scott Andrews From mtang at snf.stanford.edu Thu Oct 9 07:47:06 2003 From: mtang at snf.stanford.edu (Mary Tang) Date: Thu, 09 Oct 2003 07:47:06 -0700 Subject: SNF December Shutdown Schedule Message-ID: <3F8574EA.3AF2BDDA@snf.stanford.edu> Greetings Labmembers: No doubt, you'd all like to see the December lab shutdown schedule. Basically, it is the same as this year's University-wide shutdown... The lab will be closed to labmembers starting Friday, 12/19/03, at 7 am (SNF staff will be putting equipment to rest starting at this time). The lab will be open again to labmembers starting Monday, 1/5/04, at 4 pm (SNF staff will have been hard at work since 7 am, waking up equipment). Availability of specific equipment will be subject to pre-schedule maintenance at shutdown and process qualification on startup. Details on specific tools and activities will be posted as they come on the website at: http://snf.stanford.edu/Labmembers/Shutdown.html (linked from the SNF home page.) On behalf of the SNF staff members -- start making your holiday plans! Mary -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From guerra at par.stanford.edu Thu Oct 9 09:21:33 2003 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 9 Oct 2003 09:21:33 -0700 (PDT) Subject: EE310 Integrated Circuits Seminar, 10/14/03 In-Reply-To: Message-ID: EE310 Integrated Circuits Technology and Design Seminar "The iFlow Design Factory Infrastructure for a 17M-gate, 0.13, 333MHz Design" REX NADEN Silicon Access Networks Tuesday, October 14, 2003 4:15 p.m. Building 380, Room 380X ABSTRACT To be able to meet time-to-market requirements and solve the challenges inherent to the multi-site development of large System-on-a-Chip designs, Silicon Access Networks had to evolve a new industrial process, called the iFlow Design Factory. This contribution describes this unique infrastructure which is quality-driven rather than time-committed. The resulting chip design process is streamlined, visible, and measured, achieving predictability. Four chips were designed using TSMC's 0.13G process and collectively contain 730 million transistors, including a number of custom analog I/Os and memories. Bring-up and the first year's production proved that first silicon met all its targets: power, speed, yield, parametric compliance, and complete functionality with no mask changes required. From shott at snf.stanford.edu Thu Oct 9 13:54:45 2003 From: shott at snf.stanford.edu (John Shott) Date: Thu, 09 Oct 2003 13:54:45 -0700 Subject: Logging into sunstar/sunray/coral and you get "funny windows" ... Message-ID: <3F85CB15.6020905@snf.stanford.edu> SNF Lab Members: A number of you have occasionally experienced logging into either sunstar or sunray (the machines on which we run in-lab Coral) and getting a set of "funny looking windows". In this case, for reasons that I can't explain, you've gotten the wrong window environment. We use Common Desktop Environment and, for whatever reason, you've gotten either OpenWindows or Gnome. You can fix this very quickly .... 1. Logout from that "funny looking" session. 2. When the login window reappears (before you login again), click on the "Options" button and then select the "Session" item. 3. This will give you 5 choices (and "Users Last Desktop" should be highlighted which, in general, is correct because, normally, you want to use the same desktop everytime). This time, however, select "Common Desktop Environment (CDE)". 4. Login in normally ... you should see the desktop that you are used to and Coral should start automatically. Let me know if you have any further problems or questions, Thanks, John From dcchu at stanford.edu Thu Oct 9 22:17:21 2003 From: dcchu at stanford.edu (Dachen Chu) Date: Thu, 9 Oct 2003 22:17:21 -0700 Subject: Ph.D. Oral Defense Message-ID: <1065763041.3f8640e1386ee@webmail.stanford.edu> Department of Physics ? University Ph. D Oral Defense Thermal Management in Electron Beam Lithography and Nano-Thermocouples Dachen Chu Advisor: Professor Fabian Pease 9:00am, Thursday, Oct 16th, 2003 Packard Electrical Engineering Building, Room 101 Refreshments at 8:45am Electron Beam Lithography (EBL) in photomask fabrication results in heating of the resist films. The local heating can change the chemical properties of resist, leading to placement errors. The heating induced error has been believed to be increasingly significant as the transistor minimum feature size approaches the sub100 nm region. A Green?s function approach has been developed to calculate four- dimensional temperature profiles in complex structures such as the multi- layer work-pieces being exposed in EBL. The model is being used to characterize different ebeam writing strategies to find the optimum. To provide the parameters for the model, two independent techniques have been employed: a thin film electrode method and a laser thermal-reflectance method. Unlike earlier results from polyimide films, no appreciable anisotropy was observed in thermal conductivities for the polymeric resists tested. Gold/nickel thin film thermocouples with minimum junction area of 100nm by 100nm were fabricated and calibrated. These thermocouple demonstrated a 400ns response time when heated by a 10ns laser pulse. Using these nano thermocouples, transient resist heating temperature profiles were for the first time measured at room temperature. Experimental results showed a good agreement with the Green?s function model. We also observed a tradeoff in the scaling of thermocouple sensors. The smaller thermocouples may provide higher spatial and temporal resolutions but have poorer temperature resolution. In conclusion, we both modeled and measured the resist heating in EBL. In short exposure time (1us or less) the resist heating is nearly adiabatic, while in longer time the heating is dominated by substrate. Nano scale metallic thermocouples were explored and tradeoff was observed in dimension scaling. From rcrane at snf.stanford.edu Fri Oct 10 14:21:06 2003 From: rcrane at snf.stanford.edu (Dick Crane) Date: Fri, 10 Oct 2003 14:21:06 -0700 Subject: Recent thefts in this area Message-ID: <3F8722C2.18680149@snf.stanford.edu> Lab users and building dwellers, There has been several thefts of laptops and other small electronic devices in the last two weeks in the science/engineering side of campus. I have been requested by Stanford's Department of Public Safety to remind you to exercise prudent judgment concerning safe storage of your laptops, computers, and other valuables, not propping locked, outside doors open, and reporting any suspicious activities in or around the building. The Department of Public Safety can be reached at 3-9633 M-F 0830/1700, 329-2413 after hours, or use 9-911 in case of emergency. Thank you for your help, Dick Crane From ACREMANN at SSRL.SLAC.STANFORD.EDU Wed Oct 15 11:04:45 2003 From: ACREMANN at SSRL.SLAC.STANFORD.EDU (ACREMANN at SSRL.SLAC.STANFORD.EDU) Date: Wed, 15 Oct 2003 11:04:45 -0700 (PDT) Subject: RIE etch of SiN using a PMMA mask Message-ID: <01L1UT4W9RTE98BWAG@SSRL.SLAC.STANFORD.EDU> Hi We need to pattern a SiN film of 10nm thickness using a 100nm PMMA mask. Is there a dry etching process in which the mask survives the etching through the thin SiN layer? We can only use gold-contaminated equipment. Thanks Yves From vigneshg at stanford.edu Wed Oct 15 11:56:01 2003 From: vigneshg at stanford.edu (Vignesh G Shankar) Date: Wed, 15 Oct 2003 11:56:01 -0700 Subject: Dry etching titania Message-ID: <5.2.1.1.2.20031015115243.00b78038@vigneshg.pobox.stanford.edu> Hi, I could really use some help with some information on dry etching titania. I am in need of a fairly anisotropic etch into titania, with a large aspect ratio. I wonder if anyone has done RIE (or something else) on titania and has any info / recipes / references that might be of use to me. Thanks. - Vignesh From mtang at snf.stanford.edu Thu Oct 16 11:43:09 2003 From: mtang at snf.stanford.edu (Mary Tang) Date: Thu, 16 Oct 2003 11:43:09 -0700 Subject: XeF2 Etching Presentation Message-ID: <3F8EE6BC.3C654240@snf.stanford.edu> Greetings Labmembers -- Several labmembers have used and expressed interest in acquiring XeF2 etching capability at SNF, so we've invited David Springer, from XACTIX to give a seminar on this subject. *************************************************************** Xenon Difluoride Silicon Etch: A Key Process Technology for MEMS Manufacture Thursday, Oct. 23, 2003 CIS Room 101 (The Linville Room) Seminar 2:00pm - 3:00pm Refreshments and Discussion 3:00pm - 4:00pm A Rapidly growing number of companies and major MEMS R&D centers, including Analog Devices, Northrop Grumman, Mitsubishi, NIST, NASA, Berkeley, Cal Tech and Stanford, are using isotropic etching of silicon with xenon difluoride for MEMS release and for creating micro structures. The xenon difluoride etch is a dry, gas phase etch, highly selective to a large number of materials, which provides substantial benefits over wet or plasma etch processes. In this seminar Dr. Springer will describe the etching process and introduce some of the most recent products and research using xenon difluoride silicon etch. These will serve as examples to demonstrate the many advantages of releasing MEMS using xenon difluoride including its excellent "reach", the wide variety of materials which can now be used in manufacturing MEMS devices and the ability to integrate MEMS with electronics, perform long undercuts and release using nano-scale release holes and release layers. Refreshments will be served. David Springer is President of XACTIX, Inc, the leading supplier of xenon difluoride silicon etch equipment. David received his Ph.D. in Computer engineering from Carnegie Mellon in 2001. Before joining XACTIX David was active in the Electronic Design Automation industry including an extended period as president and founder of DASYS, Inc. which pioneered tools linking the behavioral design of ASICS and FPGAs with physical design. -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jules83 at stanford.edu Thu Oct 16 17:21:09 2003 From: jules83 at stanford.edu (Julia R Greer) Date: Thu, 16 Oct 2003 17:21:09 -0700 Subject: Si etch rate? Message-ID: Hello, I was wondering if anyone ever etched Poly-Si in Chamber A in P5000? I need to figure out my etch rate for etching 3um deep into Poly-Si... Thank you! -Julia It's all about making 83,000 Gold Nanopillars! From lian at monano.com Fri Oct 17 21:33:03 2003 From: lian at monano.com (Lian Zhang) Date: Fri, 17 Oct 2003 21:33:03 -0700 Subject: lost mask Message-ID: <005801c39530$ebe88980$596418ac@nanoprobe> Dear members, I might have lost a mask with my name (Lian Zhang) on it. It'll be really great if you can reply this message if you happened to see it. Otherwise have a nice weekend! Thanks, Lian -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Tue Oct 21 11:21:36 2003 From: mtang at snf.stanford.edu (Mary Tang) Date: Tue, 21 Oct 2003 11:21:36 -0700 Subject: Reminder: XeF2 Etch Seminar Message-ID: <3F957930.487F1688@snf.stanford.edu> Hi all -- Just a reminder of the XeF2 etch seminar, being given by David Springer of Xactix.... M *************************************************************** Xenon Difluoride Silicon Etch: A Key Process Technology for MEMS Manufacture Thursday, Oct. 23, 2003 CIS Room 101 (The Linville Room) Seminar 2:00pm - 3:00pm Refreshments and Discussion 3:00pm - 4:00pm A Rapidly growing number of companies and major MEMS R&D centers, including Analog Devices, Northrop Grumman, Mitsubishi, NIST, NASA, Berkeley, Cal Tech and Stanford, are using isotropic etching of silicon with xenon difluoride for MEMS release and for creating micro structures. The xenon difluoride etch is a dry, gas phase etch, highly selective to a large number of materials, which provides substantial benefits over wet or plasma etch processes. In this seminar Dr. Springer will describe the etching process and introduce some of the most recent products and research using xenon difluoride silicon etch. These will serve as examples to demonstrate the many advantages of releasing MEMS using xenon difluoride including its excellent "reach", the wide variety of materials which can now be used in manufacturing MEMS devices and the ability to integrate MEMS with electronics, perform long undercuts and release using nano-scale release holes and release layers. Refreshments will be served. David Springer is President of XACTIX, Inc, the leading supplier of xenon difluoride silicon etch equipment. David received his Ph.D. in Computer engineering from Carnegie Mellon in 2001. Before joining XACTIX David was active in the Electronic Design Automation industry including an extended period as president and founder of DASYS, Inc. which pioneered tools linking the behavioral design of ASICS and FPGAs with physical design. -- Mary X. Tang, Ph.D. National Nanofabrication Users' Network Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mahnaz at snf.stanford.edu Tue Oct 21 13:49:04 2003 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Tue, 21 Oct 2003 13:49:04 -0700 Subject: Bond presentation Message-ID: <3F959BC0.9B07DFC4@snf.stanford.edu> Hello all, There will be a presentation on the fundamental of bonding ( si - si and si to glass) given by staff engineer, Chad Brubaker of Electronic Vision on Wednesday October 29th at 10 am in CIS 101. We need to start promptly as I only have the Auditorium reserved till 11:30. There will be a presentation in front of the tool in the afternoon at 1:30 in the lab. I will strongly encourage all new comers to attend both presentation session. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From jerabek at snf.stanford.edu Wed Oct 22 11:24:51 2003 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Wed, 22 Oct 2003 11:24:51 -0700 (PDT) Subject: Shutdown micronic 2003-10-22 11:19:00: Report Shutdown for micronic (fwd) Message-ID: ---------- Forwarded message ---------- Date: Oct 22, 2003 11:19:01 AM From: jerabek at snf.stanford.edu To: micronic-pcs at snf.stanford.edu Subject: Shutdown micronic 2003-10-22 11:19:00: Report Shutdown for micronic Shutdown due to severe focus problem.Machine won't stay in focus even during single mask write.Called Micronic fiels eng. -Paul From jerabek at snf.stanford.edu Fri Oct 24 16:28:49 2003 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Fri, 24 Oct 2003 16:28:49 -0700 (PDT) Subject: Shutdown micronic 2003-10-22 11:19:00: Report Clear for micronic (fwd) Message-ID: ---------- Forwarded message ---------- Date: Fri, 24 Oct 2003 16:26:12 -0700 From: jerabek at snf.stanford.edu To: micronic-pcs at snf.stanford.edu Subject: Re: Shutdown micronic 2003-10-22 11:19:00: Report Clear for micronic Micronic field eng. could not find anything wrong with the machine.Yesterday afternoon it started to work correctly and has been good since then.This seems to be one of those inteminent things.Will keep an eye on it. -Paul From mahnaz at snf.stanford.edu Tue Oct 28 08:53:29 2003 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Tue, 28 Oct 2003 08:53:29 -0800 Subject: [Fwd: Bond presentation] Message-ID: <3F9E9F09.ACA0F95@snf.stanford.edu> -------------- next part -------------- An embedded message was scrubbed... From: Mahnaz Mansourpour Subject: Bond presentation Date: Tue, 21 Oct 2003 13:49:04 -0700 Size: 2596 URL: From mahnaz at snf.stanford.edu Wed Oct 29 09:21:48 2003 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Wed, 29 Oct 2003 09:21:48 -0800 Subject: presentation Message-ID: <3F9FF72C.46E722DE@snf.stanford.edu> Hello all Kind reminder that EV presentation will be at 10 am in auditorium. mahnaz From guerra at par.stanford.edu Thu Oct 30 15:40:40 2003 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 30 Oct 2003 15:40:40 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 11/4/03 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Sheerluck Ohms and the 33dB Solution" Paul Brokaw Analog Devices Tuesday, November 4, 2003 4:15 p.m. Building 380, Room 380X ABSTRACT In this presentation a basic property of the Junction Transistor will be used to deduce a connection between the Gain of a simple Amplifier and a Bandgap Voltage Reference in way that is surprisingly robust in a useful building block. The razor thin connection between the title of the presentation and the material presented, may become apparent to fans of "The Great Detective," but will likely remain a mystery, to others. From shott at snf.stanford.edu Fri Oct 31 15:18:53 2003 From: shott at snf.stanford.edu (John Shott) Date: Fri, 31 Oct 2003 15:18:53 -0800 Subject: "Old style" account numbers .... Message-ID: <3FA2EDDD.8060209@snf.stanford.edu> SNF Lab Members: As it has been a full month since the conversion to the new Project-Task-Award style account numbers, I am going to deactivate all of the "old style" account numbers (e.g., 9VAV789, 2ABC123, etc.). If you still have these in your list, and have not converted them, you will not be able to use them in the future. If these old style account numbers are the only ones you are authorized to charge to, you will not be able to login to Coral until this has been fixed. Thank you for your continued support, John From mcalarrudo at unitysemi.com Fri Oct 31 17:29:04 2003 From: mcalarrudo at unitysemi.com (Mary Calarrudo) Date: Fri, 31 Oct 2003 17:29:04 -0800 Subject: Pt etching on MRC Low Pressure Reactive Ion Etcher Message-ID: <000001c3a017$8cec3c50$1f80800a@MCalaurrudo> Labmembers, I am having a problem with uniformity when etching platinum. Has anyone else had a problem with uniformity when etching platinum, and are there any suggestions to help me with this problem. Mary Calarrudo Associate Process Engineer Unity Semiconductor Corporation 250 North Wolfe Road Sunnyvale, CA 94085 mcalarrudo at unitysemi.com 408-737-7200 x111 -------------- next part -------------- An HTML attachment was scrubbed... URL: