EE310 Integrated Circuits Seminar, 10/14/03

Ann Guerra guerra at par.stanford.edu
Thu Oct 9 09:21:33 PDT 2003


EE310 Integrated Circuits Technology and Design Seminar

"The iFlow Design Factory Infrastructure for a 17M-gate,
	   0.13, 333MHz Design"

	       REX NADEN
	 Silicon Access Networks

	Tuesday, October 14, 2003
		4:15 p.m.
	Building 380, Room 380X


		 ABSTRACT

To be able to meet time-to-market requirements and solve the challenges
inherent to the multi-site development of large System-on-a-Chip designs,
Silicon Access Networks had to evolve a new industrial process, called the
iFlow Design Factory.  This contribution describes this unique
infrastructure which is quality-driven rather than time-committed.  The
resulting chip design process is streamlined, visible, and measured,
achieving predictability.  Four chips were designed using TSMC's 0.13G
process and collectively contain 730 million transistors, including a number
of custom analog I/Os and memories.  Bring-up and the first year's
production proved that first silicon met all its targets: power, speed,
yield, parametric compliance, and complete functionality with no mask
changes required.





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