process questions

Kai Ma kaima at
Fri Apr 23 11:09:41 PDT 2004

Dear members,

I have some process questions seeking your advice. Thank you very much in
advance for your inputs!

I have a CMOS chip which is completely finished, with passivation layers.
The passivation layers are: 1um (HDP) SiO2 plus 0.4um nitride. After the
passivation, some openings (~20um by 20um big) were made to expose the
metal layer underneath for later flip-chip bonding purpose and to expose
metal contact pads. The last layer of metal that is exposed is ~1um thick,
consisted of 100A Ti, 200A TiN, 8500A Al with 0.5% Cu, and then the last
layer is 250A TiN.

What I am going to do is to grow 1um GaAs on top of the top SiN layer
using MBE. The growth process will deposit GaAs everywhere on the chip,
including inside the openings. After growth, I need to etch the GaAs grown
in the original opening area to expose metal for later contact.

My questions are:

1. Do you know how I can etch the poly-GaAs grown inside the openings,
but not to damage the metal layer (250A TiN) underneath?

2. If there exists a way to do this selective etch, great! In case it is
not possible, I am thinking to deposit a thin SiO2 layer on top first,
then grow GaAs. Because those openings were made somehow, there must be a
way to do selective etch between SiO2 and TiN. Unfortunately, the chip was made
by someone else who I lost contact. Do you know how they etched the
SiN+SiO2 layer but not to damage TiN and other metal layers?

3. Before the deposition, I hope to clean the chip a bit because it has
been sitting in air for more than a year. Do you know a way that cleans
the SiN layer but not to damage the exposed metal?

Thank you very much for your help with any of the questions!


More information about the labmembers mailing list