From guerra at par.stanford.edu Mon Feb 2 14:29:07 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Mon, 2 Feb 2004 14:29:07 -0800 (PST) Subject: SPECIAL Delft TU SEMINAR Thurs 2/19/04 Message-ID: SPECIAL SEMINAR Kofi Makinwa, Michiel Pertijs Electronic Instrumentation Laboratory Delft University of Technology Thursday Feb. 19, 2004 2:30 p.m. CISX-338 Following the seminar, the speakers would like to continue with an open discussion regarding analog/digital and sensor circuits research at Stanford. A Smart Thermal Wind Sensor ---------------------------- A 2-D wind sensor with integrated interface electronics will be presented. The sensor consists of a square chip realized in a standard CMOS process. In operation, the chip is heated to about 10oC above ambient temperature. Airflow over the packaged chip cools it in a non-uniform manner and the resulting flow-induced temperature differences are measured by on-chip thermopiles. Three thermal sigma-delta modulators control and simultaneously digitize the flow-dependent heat distribution in the chip. Since the thermopile outputs are at the microvolt level, auto-zeroing techniques are applied in the modulator circuitry. Errors in the computed wind speed and direction are less than 3% and 2 degrees respectively. A High-Accuracy CMOS Smart Temperature Sensor --------------------------------------------- A low-cost smart temperature sensor with a 3-sigma inaccuracy of +/-0.5oC from -50oC to 120oC will be presented. This sensor combines precision interface electronics, a second-order sigma-delta ADC, and a digital bus interface on a single CMOS chip. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. The temperature characteristics of these transistors and their effect on the accuracy of the sensor will be discussed. The application of curvature correction, chopping and dynamic element matching in the interface electronics will be shown. The sensor is trimmed after packaging by comparing its output with the die temperature measured using an on-chip 'calibration transistor'. Details of this low-cost technique will be presented. Kofi > > Our main goal is to get a feel for the kind of research Prof. Wooley and > > his group are currently working. We could also give some presentations > > ourselves (Smart CMOS Temperature and Flow Sensors). From rcrane at snf.stanford.edu Mon Feb 2 17:50:07 2004 From: rcrane at snf.stanford.edu (Dick Crane) Date: Mon, 02 Feb 2004 17:50:07 -0800 Subject: New etch maint. tech Message-ID: <401EFE4F.993D8666@snf.stanford.edu> Lab users, I would like to take a moment to welcome aboard Elmer Enriquez, our newest member of maintenance staff. He will be responsible for the daytime maintenance of the etch tools. Elmer comes to us after 16 years at National Semiconductor as a Senior Equipment Engineer and most recently from Andevices in Fremont. He will start at SNF on Tuesday, February 3, and his phone number is 5-3690, email address to follow. Please stop by Len's old cube in CIS155 and say hi to Elmer. Thanks, Dick Crane From shott at snf.stanford.edu Tue Feb 3 18:08:39 2004 From: shott at snf.stanford.edu (John Shott) Date: Tue, 03 Feb 2004 18:08:39 -0800 Subject: Changes in reservation policies ... Message-ID: <40205427.9090705@snf.stanford.edu> SNF Labmembers: Many of you are aware that demand for a handful of pieces of equipment has reached the crisis stage. For the raith and the stsetch, the machines are nearly completely reserved around the clock seven days in advance. Moreover there is a competition nearly every half hour for each new 30 minute slot as it becomes available ... even though on those two machines an isolated 30 minute reservation isn't terribly useful. We would like to make two changes to the current reservation rules that will, we believe, alleviate the crisis on these two machines without a significant impact on the less-heavily reserved tools in the lab. The two changes that we would like to make include: 1. Extending the allowable reservation window from 7 days to 14 days from right now. 2. Changing the rule so that rather than having the reservation END during the horizon window, the reservation will only have to START during the reservation window. (Note: this has the advantage that even if demand is high, the person who gets the reservation with the longest time window will be able to make a full, usable reservation). I'm hopeful that they two changes will make life better for folks using the raith and stsetch ... and that these changes will not have a significant impact on too much else. This all, of course, assumes that people will not hog or hoard excessive amounts of time. The Raith community has worked together to adopt some working guidelines that promote equitable sharing of a scarce resource and I applaud there community spirit in trying to do what is best for the overall community. I'm optimistic that the STS Deep Etch community will be equally community-minded in establishing voluntary guidelines. I should also tell you that Bill Murray is working hard on providing the infrastructure that will allow us to establish and to automatically enforce equipment-specific rules governing reservations within SNF. That capability, when it is released, should make further improvements in our ability to equitably share scarce resources. If you have any concerns with these changes or see problems created by them, please let me know and we will do our best to address those concerns. I expect that we should be able to make these interim changes and have them in place in the very near future ... hopefully within the next 24 hours. When that change occurs, I'll try to send out a brief e-mail alerting you to that fact. Thank you all for your consideration and, in particular, for sharing some of our scarcest equipment resources in an equitable manner. John From saraswat at cis.stanford.edu Wed Feb 4 08:52:59 2004 From: saraswat at cis.stanford.edu (saraswat) Date: Wed, 4 Feb 2004 08:52:59 -0800 Subject: SPECIAL SEMINAR REMINDER- Dr. Makimoto of Sony, on digital future In-Reply-To: References: Message-ID: <96ABA15A-5732-11D8-9E45-000A95A4F55E@cis.stanford.edu> Dr. Tsugio Makimoto Sony Corporation Friday, February 6, 2004 1:30 p.m. Cypress Semiconductor Auditorium, CISX-101 -Title: Paradigm Changes Toward Digital Consumer Products/Technology -Abstract: The chip industry is in transition from a PC centric to a DC or Digital Consumer centric industry. Digitalization of consumer electronics will have major impacts on our society creating the "Second Digital Wave." New directions in chip technologies will be presented in the new paradigm. Robotics will become the market and technology driver in the long range and "Cleverness Driven Devices" will become increasingly important. -Biography: Born on 15th May 1937, Dr. Makimoto is Corporate Advisor to Sony Corporation in charge of semiconductor technology. He received the B.S degree from the University of Tokyo in 1959, the M.S degree in 1966 from Stanford University., and the Ph.D. degree from the University of Tokyo in 1971. From 1959 to 1999, he worked at Hitachi Ltd. in the field of semiconductor. He started as a device engineer and later assumed various managerial positions including General Manager of Semiconductor Division in 1992 and finally Senior Executive Managing Director in 1997. He joined Sony as Corporate Senior Executive Vice President in 2000 and assumed the current position in 2001. In the late 1970s, he took the leadership of developing high-speed CMOS devices which marked a key turning point in the history of semiconductor industry. In the late 1980s, he discovered the cyclical nature of semiconductor industry which alternates directions between customization and standardization, roughly every ten years. This cycle was named as Makimotos Wave by the Electronics Weekly in UK. Based on this wave concept, he wrote a book Living with the Chip in 1995 jointly with D. Manners. In the 1990s, he took leadership in developing and manufacturing high density DRAMs and new types of RISC microprocessors, and was nominated an IEEE FELLOW in 1997 for his contribution for developing and manufacturing high-density MOS devices. In 1997, he wrote a book titled Digital Nomad, again with D. Manners, to introduce the new trends in the field of electronics after the PC. Dr. Makimoto gave various keynote speeches at major semiconductor related international conferences including two keynotes at IEDM in 1982 and 2002. From guerra at par.stanford.edu Wed Feb 4 10:15:06 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 4 Feb 2004 10:15:06 -0800 (PST) Subject: Slight change in 2/10 ISSCC PRESENTATIONS @ Stanford In-Reply-To: Message-ID: FOUR ISSCC presentations will now begin at 10:00 a.m. on Tuesday, February 10, CIS-101 SPECIAL SEMINAR **** FOUR ISSCC PRESENTATIONS **** IEEE International Solid-State Circuits Conference TUESDAY, FEBRUARY 10, 2004 10:00 a.m. CIS-101 "A 4uA Qulescent Current Dual-Mode Buck Converter IC for Cellular Phone Applications" J. Xiao, et. al, U. C. Berkeley ABSTRACT: This digitally-controlled buck converter IC occupies 2mm2 active area in 0.25um CMOS, and the quiescent current is 4uA, representing more than a 10-fold improvement over traditional analog apporaches. Light load efficiency is improved from 25% to 72%. Thus, cellular phone standby time can be extended by almost 3 times. "A Fourth-Order Sigma-Delta Interface for Micromachined Inertial Sensors" V. Petkov and B. Boser, U. C. Berkeley ABSTRACT: A high-order electromechanical sigma-delta modulator uses additional electronic filtering in the loop to eliminate excessive in-band quantization noise inherently present in second-order implementations. The interface is fabricated in a 0.5um CMOS process and tested with a gyroscope and accelerometer achieving 1deg/s/rootHz and 150ug/rootHz of resolution, repsectively. Active chip area is 0.9mm2 and the IC consumes a total of 18mW. "An 800mW 10Gb Ethernet Transceiver in 0.13um CMOS" S. Sidiropoulos, et. al; Aeluros presented by Arnold Feldman ABSTRACT: A fully integrated 10Gb Ethernet transceiver IC using a standard 0.13um CMOS process integrates 10.3Gb/s and 4x3.12Gb/s analog front-ends, with Layer-1 coding and management functionality. The 2.5x5mm2 IC exceeds both 10GE and SONET specifications, and dissipates 800mW from its 1.2/2.5V supplies. "A 1.8V 14b 10MS/s Pipelined ADC in 0.18um CMOS with 99dB SFDR" Y. Chiu, P. Gray, B. Nikolic; U. C. Berkeley presented by Yun Chiu ABSTRACT: A 1.8V, 14b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99dB SFDR for signal frequencies up to 5.1MHz without trimming or calibration. With a 1MHz analog input, DNL is 0.31LSB, INL is 0.58LSB, and SNDR is 73.6dB. The chip occupies 15mm2 in 0.18um CMOS and dissipates 112mW. From grupp at snowmass.Stanford.EDU Wed Feb 4 12:54:03 2004 From: grupp at snowmass.Stanford.EDU (Dan Grupp) Date: Wed, 4 Feb 2004 12:54:03 -0800 (PST) Subject: FINAL PLEA FOR MISSING WAFERS Message-ID: If you have them (a big white plastic cassette box of 8" wafers from SiGen/Acorn with 3 wafers) you can still return them for a big reward. If you have them and are too embarrassed to return them, or worried about retribution, just leave them where someone else can find them. In the hall outside the fab on a bench is ok. Anywhere reasonable in the building in plain view where a labmember can spot them. Still too risky? Leave them anywhere on the planet in plain site (closer is better, like over at Bytes Cafe) with a note to call me if found! If they are broken, I still want them. pieces are fine. Is it clear yet how important these wafers are to me? Thanks, Dan --------------------------------------------------------------------------- Dr. Daniel Grupp, Visiting Scholar Center for Integrated Systems Stanford University Stanford, CA 94305 (650) 724-6911 FAX: 723-4659 --------------------------------------------------------------------------- From mahnaz at snf.stanford.edu Thu Feb 5 17:11:56 2004 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Thu, 05 Feb 2004 17:11:56 -0800 Subject: Down time Message-ID: <4022E9DC.27FF88CC@snf.stanford.edu> Hello all, We need to put the singe oven down tomorrow morning. Thanks to some one whom ran wafers with resist, there are many little particles in the oven so we need to cool the oven, check the filter and clean it. One lab member's work needed to be reworked due to particles. You may not put wafers with resist in the singe or Yes oven at all. If you have any question or concern see me, we are only on the second month of the year. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From rgrow at stanford.edu Fri Feb 6 13:56:32 2004 From: rgrow at stanford.edu (Randy Grow) Date: Fri, 6 Feb 2004 13:56:32 -0800 Subject: Young's Modulus for LONH378? Message-ID: <535A4268-58EF-11D8-8A22-000393910ACA@stanford.edu> Hi, I was wondering if anyone has measured the Young's modulus and Poisson's ratio for the LPCVD low-stress silicon nitride, in particular the old recipe, LONH378? I didn't find any mention of it on the website. Thanks, Randy From mahnaz at snf.stanford.edu Fri Feb 6 15:07:40 2004 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Fri, 06 Feb 2004 15:07:40 -0800 Subject: Singe oven Message-ID: <40241E3C.5DBA0C4A@snf.stanford.edu> Hello all The singe oven has been cleaned and baking as of right now the system will be available after 5 pm today 1/6/04. Please do not put any wafers with resist in the singe oven that will out gas and cause all sort of problem for other labmembers and the oven. Mario/Mike and Mahnaz From guerra at par.stanford.edu Fri Feb 6 16:01:42 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Fri, 6 Feb 2004 16:01:42 -0800 (PST) Subject: Reminder Atheros SPECIAL ICL SEMINAR 2/9/04 Message-ID: MONDAY, FEBRUARY 9, 2004 10:00 a.m. CIS-101 "A Single-Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE 802.11a/b/g/ WLAN" M. Zargari, et. al. (co-authors from Atheros, IRF, and Stanford) presented by Masoud Zargari, Atheros Communications ABSTRACT: A 2.4/5GHz transceiver implements the RF and analog front-end of an IEEE 802.11 a/b/g WLAN system in 0.25um CMOS technology. The IC transmits 9dBm/8dBm EVM-compliant output power at 5GHz/2.4GHz for a 64QAM OFDM signal. The overall receiver NF is 5.5/4.5dB at 5/2.4GHz. AND "A 3.2 to 4GHz 0.25um CMOS Frequency Synthesizer for IEEE 802.11 a/b/g WLAN" M. Terrovitis, M. Mack, K. Singh, M. Zargari Atheros Communications presented by Manolis Terrovitis ABSTRACT: A fully integrated 3.2 to 4GHz frequency synthesizer, part of an IEEE 802.11 a/b/g/ transceiver, is implemented in a 0.25um standard CMOS technology. The phase noise is -105dBc/Hz at 10kHz offset, and the spurs are below -64dBc when measured at the 5GHz transmitter output. The settling time is less than 150us. From shott at snf.stanford.edu Mon Feb 9 05:40:13 2004 From: shott at snf.stanford.edu (John Shott) Date: Mon, 09 Feb 2004 05:40:13 -0800 Subject: Changes to the Coral reservation horizon ... Message-ID: <40278DBD.2080501@snf.stanford.edu> SNF Labmembers: I've received significant feedback related to the proposed changes to the reservation system. Most were concerned that allowing the reservation horizon to expand from 7 to 14 days was too big a jump. At the same time, I feel that there is a strong need to do something to alleviate the serious problems that we have on a handful of tools ... with the Raith and the STS deep etcher leading the way in terms of overall demand. The Raith community has been particularly proactive in terms of discussing and arriving at a self-imposed set of reservation limits. I applaud their community-minded efforts and want to do the best that we can in supporting them with appropriate changes within Coral. They have adopted a set of reservation rules that will go in effect shortly after midnight on Monday night ... well, technically at 12:01 a.m. on Tuesday morning. The Coral servers will be restarted at that time with the following changes to the reservation server: 1. The reservation horizon will be increased from 7 days to 10 days. 2. Reservations must start (rather than end) within that reservation horizon. This change, in particular, is designed to avoid the "30-minute roulette" that labmembers wishing to reserve the raith and the stsetch have been forced to play. The risk of this last change may be folks "hogging" reservations at the end of the reservation horizon. If unreasonable hogging occurs, I believe that we can deal with that in two ways. First, I'm hopeful that the tools with high demand for reservations will follow the lead of the Raith community and work to establish reasonable guidelines for maximum equipment reservations. The appropriate equipment mailing list should be a good way to start these discussions. Secondly, obvious reservation hogging, particularly if it violates generally understood reservation guidelines for a particular tool, will result in the deletion of the offending reservations. While rules related to duration of reservations are currently not enforced automatically in Coral, Bill Murray is working hard on adding the capability to define and enforce equipment-specific reservation rules. While that capability is not near release, it is our highest current priority. In the meantime, the development of community-based reservation rules (for those pieces of equipment that warrant them) will both help to better share scarce resources now and will allow us to experiment to find appropriate rules in anticipation of our ability to automatically enforce them. If you have feedback related to how these new reservation rules affect the operation of SNF as you gain experience with these changes, please make sure to contact me. Thank you for your continued support, John Remember, the reservation horizon will increase from 7 to 10 days near midnight on Monday night. From harshal at snf.stanford.edu Tue Feb 10 13:50:14 2004 From: harshal at snf.stanford.edu (Harshal Surangalikar) Date: Tue, 10 Feb 2004 13:50:14 -0800 Subject: STS time policy. Message-ID: <40295216.5040009@snf.stanford.edu> dear STS users, i wanted to make a few comments about the new reservation policy for the STS users. 1) if i am not wrong, (and please correct me if i am!) the "advance" time period has now been increased from 7 days to 10 days, and 2) the limit on the reservation slot has been removed, so that a user can now reserve the machine for as much time as he wants. i dont see how these two changes will make the situation better. on the contrary these two changes are like a double-blow and counter productive, not even, lets say, balancing each other. earlier, the advance time was 7 days and one would plan his work for 7 days so that he is able to use the time slot he has reserved. now the user has to plan his work for 10 days which is difficult than planning for 7 days since its easier to follow the plans in the near future than far. so if something goes wrong in processing, and the user is not ready for his precious time slot, he has to wait another 10 days instead of 7. secondly, now that a user can book as much as he wants, he is always going to give himself a degree of freedom to block a fat time slot. that means if i am a fraction of a second late in making the reservation, i am "out of competition" for an indefinite period of time. earlier , with the 30 min. limit on the reservation slot, i knew that i have another chance after 30 min. this also means that now for the next available time slot, there will be even more number of users fighting for 'their" big slot, compared to a fewer number of users fighting for smaller 30 min time slots at a given point of time. what can be done is: 1) we reduce the "advance" time period for reservation from 10 to 3 or 4 days so that that users are better able to plan and finish their work so as to be ready for their time slot, since its much easier to see 4 days ahead than 10 days, and 2) increase the time slot limit from 30 min to 1 hr. or 1.5 hrs. or lets say, 2 hrs. because thats the time in which a user can get something done on his current wafer comfortably and will require less rearrangements with other users. hope this makes sense and any and every input will be helpful. harshal. -------------- next part -------------- An embedded message was scrubbed... From: Harshal Surangalikar Subject: STS time policy. Date: Tue, 10 Feb 2004 13:35:47 -0800 Size: 2693 URL: From goldhaber-gordon at stanford.edu Tue Feb 10 23:20:11 2004 From: goldhaber-gordon at stanford.edu (David Goldhaber-Gordon) Date: Tue, 10 Feb 2004 23:20:11 -0800 Subject: STS time policy. In-Reply-To: <40295216.5040009@snf.stanford.edu> Message-ID: <003f01c3f06f$7c63d7a0$d26a40ab@kondolam> Dear Harshal, Thank you for your comments. At the moment, SNF can only control the reservation policy globally on Coral (i.e. all machines must have the same advance window available for reservations). The changes the administration made look very positive for the Raith system, and I expect they can be just as positive for the STS community, but only with additional community-determined rules. Without such additional rules, I agree that the situation is (and was) a disaster. The Raith community has quite productively agreed to limit our future reservations to 8 hours total per person. This is a limit on reservations, not on usage per unit time. Once one begins using a reservation, one may immediately book another, so there is in principle no limit to an individual's usage per week if the machine is not being heavily used. These limits are not currently enforced on Coral, but as a community we remind people when they have inadvertently reserved too much time. Such errors are already the exception, not the rule. I encourage you to get together as a community and draft an analogous set of agreements that work for you. Best wishes, David ---------------------------------------------------------------------------- David Goldhaber-Gordon goldhaber-gordon at stanford.edu Assistant Professor of Physics davidg at post.harvard.edu Stanford University (permanent forwarding) www.goldhaber-gordon.com (650) 725-2047 (lab) (650) 724-3709 (office) Address for letters or packages: Administrative Associate: David Goldhaber-Gordon Roberta Edwards Geballe Laboratory for Advanced Materials McCullough, Rm. 338 McCullough Building, Room 346 Phone: (650) 723-8028 476 Lomita Mall Fax: (650) 724-3681 Stanford, CA 94305-4045 email: redward at stanford.edu -----Original Message----- From: Harshal Surangalikar [mailto:harshal at snf.stanford.edu] Sent: Tuesday, February 10, 2004 1:50 PM To: labmembers at snf.stanford.edu Subject: STS time policy. dear STS users, i wanted to make a few comments about the new reservation policy for the STS users. 1) if i am not wrong, (and please correct me if i am!) the "advance" time period has now been increased from 7 days to 10 days, and 2) the limit on the reservation slot has been removed, so that a user can now reserve the machine for as much time as he wants. i dont see how these two changes will make the situation better. on the contrary these two changes are like a double-blow and counter productive, not even, lets say, balancing each other. earlier, the advance time was 7 days and one would plan his work for 7 days so that he is able to use the time slot he has reserved. now the user has to plan his work for 10 days which is difficult than planning for 7 days since its easier to follow the plans in the near future than far. so if something goes wrong in processing, and the user is not ready for his precious time slot, he has to wait another 10 days instead of 7. secondly, now that a user can book as much as he wants, he is always going to give himself a degree of freedom to block a fat time slot. that means if i am a fraction of a second late in making the reservation, i am "out of competition" for an indefinite period of time. earlier , with the 30 min. limit on the reservation slot, i knew that i have another chance after 30 min. this also means that now for the next available time slot, there will be even more number of users fighting for 'their" big slot, compared to a fewer number of users fighting for smaller 30 min time slots at a given point of time. what can be done is: 1) we reduce the "advance" time period for reservation from 10 to 3 or 4 days so that that users are better able to plan and finish their work so as to be ready for their time slot, since its much easier to see 4 days ahead than 10 days, and 2) increase the time slot limit from 30 min to 1 hr. or 1.5 hrs. or lets say, 2 hrs. because thats the time in which a user can get something done on his current wafer comfortably and will require less rearrangements with other users. hope this makes sense and any and every input will be helpful. harshal. From mcvittie at snf.stanford.edu Wed Feb 11 09:22:47 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Wed, 11 Feb 2004 09:22:47 -0800 Subject: Local AVS Conference March 1-3 Message-ID: <402A64E7.BD1E75DA@snf.stanford.edu> Lab Members, The AVS Fifth International Conference on Microelectronics and Interfaces (ICMI) will be held March 1?3, 2004, at the Santa Clara Convention Center in Santa Clara, California. ICMI provides a unique opportunity for microelectronic process and integration specialists to gather and discuss challenges facing fabrication of microelectronic and nanoelectronic circuits. Developing and integrating deposition, etching, polishing, and cleaning processes for both transistor and interconnect formation are considered. Analytical and new metrology techniques are given special consideration. Presentations range from practical ways to boost the yield of today?s devices to fundamental science and leading-edge research exploring techniques for fabricating devices of the future. You can see the full program at http://www.avs.org/conferences/icmi/2004/ Invited Talks Plenary Session R. Chau, Intel Corp., USA, Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors T. Kenny, Stanford Univ., USA, Advanced Cooling for ICs T. Schenkel, LBNL, USA, Towards Quantum Information Processing with Impurity Spins in Silicon Metrology E. Lifshin, Univ. of Albany, USA, Metrology Challenges of Nanotechnology W. Yun, Xradia, Inc, USA, Tabletop X-ray Microscope for 3D IC Imaging Chemical Mechanical Polishing I and II C. Hong, Samsung Electronics Co.,Ltd., Korea, Issues in CMP Technology and Future Challenges for Sub-100nm Devices Y. Uda, Nikon Corp., Japan, Ultra-Low Pressure Cu CMP L. Borucki, Intelligent Planar, USA, Thermal Effects During Cu CMP, J-G. Park, Hanyang University, Korea, Effect of Slurry Chemistry on Electrochemical and Frictional Behavior in Cu CMP S. Raghavan, Univ. of Arizona, USA, Dissolution Characteristics of Ceria for Post-CMP Clean Applications P. Huang, Seagate Technology Inc., USA, CMP Advances in the Magnetic Storage Industry Y. Li, Clarkson Univ., USA, The Characterization of Advanced STI CMP Processes and Consumables R. Dauskardt, Stanford Univ., USA, Effect of Complex CMP Aqueous Environments on Accelerated Cracking and Reliability Effect of Complex CMP Aqueous Environments on Accelerated Cracking and Reliability of Ultra low-k Dielectric Materials K. Reinhardt, USA, Advances in Post-CMP Cleaning Technology High-k Dielectrics and Gate Oxides B. Rogers, Vanderbilt Univ. USA, Nucleation and Growth of High K Gate Dielectrics A. Miller, Lam Research Corp., USA, Selectivity Studies of Hafnium Oxide Etch for Gate Applications A. Demkov, Motorola, Inc, USA, Theoretical Analysis of High-K Dielectric Interfaces with Silicon and Metals Contacts C. Lavoie, IBM T.J. Watson Research Center, USA, From CoSi2 to NiSi Contacts: Advantages and Limitations M. Zhang, Univ. of Illinois-Urbana, USA, TEM and Nanocalorimetry of Au Silicide Interconnects C.-K. Hu, IBM T. J. Watson Research Center, USA, Reliability of Cu metallization P.A. Burke, LSI Logic, USA, Meeting the ITRS Roadmap for Copper and Low-k BEOL Interconnect H. Cui, , LSI Logic, USA, Ultra Low-Dielectric Constant Materials for ULSI Damascene Copper Interconnect: Challenges and Opportunities J. Smythe, Micron Technology, Inc., USA, Low-K Spin-On Dielectrics for Memory Applications Etch/Plasma I.W. Rangelow, University of Kassel, Germany, High Aspect Ratio Silicon Etching P.L.G. Ventzek, Motorola, Inc., USA, Plasma Process Modeling: Computational Process Integration Perspective M.J. Cooke, Oxford Instruments, UK, ICP Technology for Etching: Source Design and Performance Cleans O. Louveau, STMicroelectronics, Plasma and Supercritical CO2 Strip of Photoresist Over Porous Low K Materials A. Busnaina, Northeastern Univ., USA, The Removal of Nanoparticles from Deep Trenches K. Reinhardt, Novellus, USA, Post CMP Cleans Prior to 2/25/04 Registration Costs are: Member $350.00 Non-Member $425.00 Student Member $100.00 Student Non-Member $110.00 ** Lunch and Hardbound Proceedings containing the extended papers are included in the registration fee** -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From miraflor at cis.stanford.edu Wed Feb 11 10:27:59 2004 From: miraflor at cis.stanford.edu (Carmen Miraflor) Date: Wed, 11 Feb 2004 10:27:59 -0800 Subject: Reminder: PHILIPS EINDHOVEN - visit & presentation 2/11 Message-ID: > > >Subject: PHILIPS EINDHOVEN - visit & presentation 2/11 >Status: RO > > >SPECIAL VISIT & PRESENTATION by PHILIPS RESEARCH, EINDHOVEN > >Wednesday, February 11, 2004 > >Three scientists from Philips Research, >Kathleen Philips, Bas Putter and Ed v Tuijl, >will visit CIS. > >At 11.00 a.m. in CIS-101 they will give an overview of their work at >Philips Research on AD and DA conversion. > >After lunch, the scientists will be available for further discussions in >CIS-101. REFRESHMENTS SERVED. -- ======^======^======^======^======^=====^=====^=====^=====^===== Carmen Miraflor, Programs Manager Center for Integrated Systems, Stanford University Stanford, CA 94305-4070 Phone: (650) 725-3617**Fax: (650) 725-0991**Email: miraflor at cis.stanford.edu ======^======^======^======^======^=====^=====^=====^=====^===== -------------- next part -------------- An HTML attachment was scrubbed... URL: From goldhaber-gordon at stanford.edu Wed Feb 11 11:34:21 2004 From: goldhaber-gordon at stanford.edu (David Goldhaber-Gordon) Date: Wed, 11 Feb 2004 11:34:21 -0800 Subject: Allocating scarce resources: one more comment In-Reply-To: <40295216.5040009@snf.stanford.edu> Message-ID: <003001c3f0d6$0c3bd060$d26a40ab@kondolam> Hi all, One more comment on allocating usage of machines that have traditionally been booked 24/7: A community agreement which allows reservations far into the future must (in equilibrium) automatically provide some unreserved time in the allowed reservation window, ideally only a few days in advance. The simple policies adopted by the Raith user community at Stanford should achieve this, though we need a couple of weeks to see how it plays out. If some open time is automatically preserved in the near future (because heavy users are restricted from snapping up that open time), it becomes unnecessary for users to plan a week or more in advance, or to fight over half hour slots as they come up. I hope this addresses Harshal's concerns, but the STS community will have to decide (discover) for itself what kind of usage restrictions will optimize access to their scarce equipment resource. Most people will have to make some sort of compromise to make it work -- after all, this is an overcommitted resource -- but I'm confident that it can be made worthwhile for the community. My group does not use the STS, but we do use the Innotec evaporator, and I would urge that a similar discussion take place in that user community. Best, David -----Original Message----- From: Harshal Surangalikar [mailto:harshal at snf.stanford.edu] Sent: Tuesday, February 10, 2004 1:50 PM To: labmembers at snf.stanford.edu Subject: STS time policy. dear STS users, i wanted to make a few comments about the new reservation policy for the STS users. 1) if i am not wrong, (and please correct me if i am!) the "advance" time period has now been increased from 7 days to 10 days, and 2) the limit on the reservation slot has been removed, so that a user can now reserve the machine for as much time as he wants. i dont see how these two changes will make the situation better. on the contrary these two changes are like a double-blow and counter productive, not even, lets say, balancing each other. earlier, the advance time was 7 days and one would plan his work for 7 days so that he is able to use the time slot he has reserved. now the user has to plan his work for 10 days which is difficult than planning for 7 days since its easier to follow the plans in the near future than far. so if something goes wrong in processing, and the user is not ready for his precious time slot, he has to wait another 10 days instead of 7. secondly, now that a user can book as much as he wants, he is always going to give himself a degree of freedom to block a fat time slot. that means if i am a fraction of a second late in making the reservation, i am "out of competition" for an indefinite period of time. earlier , with the 30 min. limit on the reservation slot, i knew that i have another chance after 30 min. this also means that now for the next available time slot, there will be even more number of users fighting for 'their" big slot, compared to a fewer number of users fighting for smaller 30 min time slots at a given point of time. what can be done is: 1) we reduce the "advance" time period for reservation from 10 to 3 or 4 days so that that users are better able to plan and finish their work so as to be ready for their time slot, since its much easier to see 4 days ahead than 10 days, and 2) increase the time slot limit from 30 min to 1 hr. or 1.5 hrs. or lets say, 2 hrs. because thats the time in which a user can get something done on his current wafer comfortably and will require less rearrangements with other users. hope this makes sense and any and every input will be helpful. harshal. From chen0622 at yahoo.com Fri Feb 13 08:00:11 2004 From: chen0622 at yahoo.com (chih-chang) Date: Fri, 13 Feb 2004 08:00:11 -0800 (PST) Subject: need information for 6 inch MEMS foundry service around bay area Message-ID: <20040213160011.73311.qmail@web12703.mail.yahoo.com> Dear Lab-members, I am looking for information on 6 inch MEMS foundry service around bay area with sub-micron process capacity. Thanks in advance for anybody providing me this information. Best regards, Chih-Chang Chen -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Thu Feb 19 10:41:29 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 19 Feb 2004 10:41:29 -0800 (PST) Subject: Reminder -- SPECIAL Delft TU SEMINAR 2:30 today Message-ID: SPECIAL SEMINAR Kofi Makinwa, Michiel Pertijs Electronic Instrumentation Laboratory Delft University of Technology Thursday Feb. 19, 2004 2:30 p.m. CISX-338 Stanford University, Center for Integrated Systems Annex, 3rd Floor Following the seminar, the speakers would like to continue with an open discussion regarding analog/digital and sensor circuits research at Stanford. A Smart Thermal Wind Sensor ---------------------------- A 2-D wind sensor with integrated interface electronics will be presented. The sensor consists of a square chip realized in a standard CMOS process. In operation, the chip is heated to about 10oC above ambient temperature. Airflow over the packaged chip cools it in a non-uniform manner and the resulting flow-induced temperature differences are measured by on-chip thermopiles. Three thermal sigma-delta modulators control and simultaneously digitize the flow-dependent heat distribution in the chip. Since the thermopile outputs are at the microvolt level, auto-zeroing techniques are applied in the modulator circuitry. Errors in the computed wind speed and direction are less than 3% and 2 degrees respectively. A High-Accuracy CMOS Smart Temperature Sensor --------------------------------------------- A low-cost smart temperature sensor with a 3-sigma inaccuracy of +/-0.5oC from -50oC to 120oC will be presented. This sensor combines precision interface electronics, a second-order sigma-delta ADC, and a digital bus interface on a single CMOS chip. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. The temperature characteristics of these transistors and their effect on the accuracy of the sensor will be discussed. The application of curvature correction, chopping and dynamic element matching in the interface electronics will be shown. The sensor is trimmed after packaging by comparing its output with the die temperature measured using an on-chip 'calibration transistor'. Details of this low-cost technique will be presented. Kofi > > Our main goal is to get a feel for the kind of research Prof. Wooley and > > his group are currently working. We could also give some presentations > > ourselves (Smart CMOS Temperature and Flow Sensors). From pease at cis.stanford.edu Thu Feb 19 16:53:35 2004 From: pease at cis.stanford.edu (Fabian Pease) Date: Thu, 19 Feb 2004 16:53:35 -0800 Subject: Microlithography Course EE317 Message-ID: <5.1.0.14.2.20040219164335.01b905b0@cis.stanford.edu> EE 317, to be offered this Spring, is reverting to being devoted entirely to microlithography. We are fortunate in having Dr. Robert Socha of ASM Lithography to be one the instructors. Dr. Socha's PhD, from UC Berkeley in 1997, was in the area of simulating aerial images in photolithographic steppers. He has continued that work at ASM Lithography where he is their lead researcher in pushing the resolution limit of optical lithography beyond the Rayleigh criterion. We are very fortunate in securing his participation in the course. Fabian Pease Instructor EE317 From xjzhang at stanford.edu Mon Feb 23 12:34:57 2004 From: xjzhang at stanford.edu (John X.J. Zhang) Date: Mon, 23 Feb 2004 12:34:57 -0800 Subject: Orals Xiaojing (John X.J.) Zhang Message-ID: <4.3.2.7.2.20040223123402.02286a38@xjzhang.pobox.stanford.edu> >Department of Electrical Engineering _ University Ph.D. Oral Defense > >Micromachined Silicon Diffractive Optical Encoder Force Sensors: >Principle and Applications in Biology >Xiaojing (John X.J.) Zhang >Ph.D. Candidate, Electrical Engineering >Advisor: Professor Olav Solgaard > >4:15pm, Monday, March 1, 2004 >Edward L. Ginzton Laboratory, AP200 >Refreshments Start at 4:00 pm > >Miniaturized instruments for injection and positioning of single cells and >embryos are becoming increasingly important in biological and genetic >studies. Localized and accurate microinjection of genetic material into >biological model systems, such as Drosophila, will enable a variety of >studies in developmental biology and genetics. For such studies to be >carried out in-vivo, the damage caused by the injection must be minimized. >We study the force required for penetration and injection into Drosophila >embryos using surface micromachined silicon-nitride probe with integrated, >micrograting-based force sensors. The probe is supported by springs of >known spring constant, and the penetration force is determined from >displacement measurements using a high-resolution, miniaturized optical >encoder that is designed to only be sensitive to axial deflections of the >probe. The encoder is based on transmission phase gratings to optimize >optical throughput. Tunability of the sensor can be achieved by either >using arrays of integrated optical encoders with various pitch, or by >varying the size of the optical beam on the encoder. The periodicity of >the encoder response can be used for calibration of the injector >displacement and to obtain information about the elastic properties of the >target. We used a force sensor with a measured spring constant of 1.85 N/m >for static penetration experiments on Drosophila embryos, and found a >penetration force of 52.5 ?N (?13.2%) and a membrane displacement of 58 ?m >(?5.2%). Using a piezoelectric actuator to vibrate the probe >longitudinally, we found that the penetration force to be reduced by 3.6 >?N with every 0.1 m/s tip velocity increase. > >We also demonstrated microfluidic self-assembled immobilization of >Drosophila embryos in 2-D arrays, which facilitates parallel, >high-throughput microinjections, and measure the positioning force acting >on the embryos in the array. The positioning force is the most critical >parameter in determining alignment errors, which in turn determines >whether acceptable injection yields can be achieved. We operate the >optical-encoder force sensor in reflection to characterize the positioning >forces, and to study shape-matching, alignment tolerance and hysteresis of >the self-assembly process as a function of pad geometry. An extended >surface energy model is developed for simulations of the positioning >forces and the affiliated potential energy wells created by the oil-based >fluidic system between the ellipsoidal embryo and the flat pad. Both >experimental and simulation results show a linear-spring like relationship >between the force and displacement of the embryos, in contrast to the >constant positioning force profile observed for self-assembly of flat >silicon pieces. The optical MEMS encoder force sensor is shown to be a >versatile tool enabling high precision probing and efficient manipulation >of single cells and embryos on-chip for a wide range of applications. ------------------------------------------------------ John X.J. Zhang, Ph.D. Candidate Department of Electrical Engineering Stanford University, CA 94305 Mail: S-50, Ginzton Lab Mobile: 408-421-9632 ------------------------------------------------------ -------------- next part -------------- An HTML attachment was scrubbed... URL: From pruitt at stanford.edu Mon Feb 23 23:47:47 2004 From: pruitt at stanford.edu (Beth Pruitt) Date: Mon, 23 Feb 2004 23:47:47 -0800 Subject: Seminar: Resists for nanoimprint lithography and SU-8 Message-ID: <5.1.0.14.2.20040223233418.0155de10@pruitt.pobox.stanford.edu> SPECIAL SEMINAR on Ultrathick and Ultrathin resists TUESDAY Feb 24 4pm in CISX Auditorium Photoresists for nanoimprint lithography and Processing of thick SU-8 visitor Dr. Freimut Reuther of micro resist technology (mrt) GmbH will discuss the following: Overview on polymers for nanoimprint lithography (NIL) of (characteristics, behaviour, basic processing considerations) Overview on high thickness positive tone photoresists Purpose and benefits of IR baking of high thickness photoresists and baking examples including positive photoresists and SU-8 SNF recently obtained EV nanimprint lithography equipment and several labmembers have been using SU-8 for mixed applications with varying results. If you have questions or are thinking of using these materials, please attend this seminar and discuss with our visitor from mrt in Berlin. -------------- next part -------------- An HTML attachment was scrubbed... URL: From ankurjn at stanford.edu Wed Feb 25 10:11:14 2004 From: ankurjn at stanford.edu (Ankur Jain) Date: Wed, 25 Feb 2004 10:11:14 -0800 (PST) Subject: anyone has experience with Spin-on-Glass? Message-ID: hi everyone: I am drwaing out a process plan in which I might use Spin-on-Glass on silicon wafers. Is there someone out there who has experience using Spin-on-Glass (SOG)? I would really appreciate if you could help me with a few queries about SOG processing. thanks in advance! Ankur ************************************************************************* ANKUR JAIN Graduate Student Residence: Microscale Heat Transfer Laboratories 19 Comstock Circle Apt. A Room 201, Building 530 Stanford University Stanford University, CA-94305 CA - 94305 Ph: 650-736-0044 Ph: 650-497-1784 http://www.stanford.edu/~ankurjn From sanli at stanford.edu Wed Feb 25 17:20:19 2004 From: sanli at stanford.edu (Arif Sanli Ergun) Date: Wed, 25 Feb 2004 17:20:19 -0800 Subject: epitaxial silicon Message-ID: <5.2.1.1.2.20040225171823.00b4bb48@sanli.pobox.stanford.edu> Hi everybody, Do any of you know companies that grow epitaxial silicon on SOI wafers in the bay area or elsewhere? Sanli From mahnaz at snf.stanford.edu Thu Feb 26 14:41:33 2004 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Thu, 26 Feb 2004 14:41:33 -0800 Subject: Yes Message-ID: <403E761D.A2E6FBF9@snf.stanford.edu> Hello all, Sorry for the short notice, Yes oven will go down for the PM tomorrow Friday 27th. Please use the singe oven for 1/2 hour before spin. mahnaz From chquay at MtHolyoke.edu Thu Feb 26 23:25:03 2004 From: chquay at MtHolyoke.edu (Charis Quay Huei Li) Date: Fri, 27 Feb 2004 02:25:03 -0500 (EST) Subject: Mysterious Leaking Oxide Message-ID: Hi guys, I'm having problems with some of my wafers having oxides that leak and was wondering if any of you had encountered this problem? Here's the relevant info: Source of wafer: Virginia Semiconductor Orientation: <111> Dopant: Antimony Resistance: 1-5mOhm Process: 1. Oxide on back etched with BOE. Front side coated with 100nm PMMA. Back side evaporated with 100nm Ti, then annealed in RTA at 350 C for 30 s. No leakage, i.e. in excess of 10GOhm. 2. AFTER step 1, chips were placed in furnace at 950 C with hydrogen flowing. Leakage observed, i.e. several hundred kOhm. Note: Leakage was tested by evaporating metal pads on front side of chips with shadow mask. I then measured the resistance between the pads on the front side and the back gate. (In case 2, it didn't matter whether I probed the bare silicon or the metal pads. Everything was shorted.) Any clues? Thanks! Cheers, Charis. From goldhaber-gordon at stanford.edu Fri Feb 27 09:14:19 2004 From: goldhaber-gordon at stanford.edu (David Goldhaber-Gordon) Date: Fri, 27 Feb 2004 09:14:19 -0800 Subject: Mysterious Leaking Oxide In-Reply-To: Message-ID: <001b01c3fd55$2339e4b0$d26a40ab@kondolam> Two additional facts for problem-solvers: Oxide thickness 500 nm, grown thermally (that's all the info we have about the oxide) -David -----Original Message----- From: Charis Quay Huei Li [mailto:chquay at MtHolyoke.edu] Sent: Thursday, February 26, 2004 11:25 PM To: labmembers at snf.stanford.edu Subject: Mysterious Leaking Oxide Hi guys, I'm having problems with some of my wafers having oxides that leak and was wondering if any of you had encountered this problem? Here's the relevant info: Source of wafer: Virginia Semiconductor Orientation: <111> Dopant: Antimony Resistance: 1-5mOhm Process: 1. Oxide on back etched with BOE. Front side coated with 100nm PMMA. Back side evaporated with 100nm Ti, then annealed in RTA at 350 C for 30 s. No leakage, i.e. in excess of 10GOhm. 2. AFTER step 1, chips were placed in furnace at 950 C with hydrogen flowing. Leakage observed, i.e. several hundred kOhm. Note: Leakage was tested by evaporating metal pads on front side of chips with shadow mask. I then measured the resistance between the pads on the front side and the back gate. (In case 2, it didn't matter whether I probed the bare silicon or the metal pads. Everything was shorted.) Any clues? Thanks! Cheers, Charis. From martinez at snf.stanford.edu Fri Feb 27 15:19:04 2004 From: martinez at snf.stanford.edu (Mike Martinez) Date: Fri, 27 Feb 2004 15:19:04 -0800 Subject: yes oven Message-ID: <403FD068.3756B42A@snf.stanford.edu> The yes oven is up and ready for use. The vapor prime program has been modified to sound an alarm if the vacuum set point of 1 torr is not met before the prime step begins. The system will remain in alarm mode until the reset button is pressed. mm From sjim at stanford.edu Fri Feb 27 16:36:51 2004 From: sjim at stanford.edu (Sungjun Im) Date: Fri, 27 Feb 2004 16:36:51 -0800 Subject: Secco etching of poly Si Message-ID: Does anyone have experience with 'Secco etching [2mL HF, 1mL K2Cr2O7 (0.15M)]' ? I am trying to delineate surface grain boundaries of poly Si (28 um). Thanks. Sungjun Im Ph.D. Candidate Department of Materials Science and Engineering Stanford University, Building 530, Room 201 440 Escondido Mall, Stanford, CA 94305-3030 Tel: (650) 736-0044 Fax: (650) 723-7657 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rcrane at snf.stanford.edu Fri Feb 27 13:15:41 2004 From: rcrane at snf.stanford.edu (Dick Crane) Date: Fri, 27 Feb 2004 13:15:41 -0800 Subject: Lab Evacuation Message-ID: <403FB37D.984F82D7@snf.stanford.edu> Lab members, On Wednesday afternoon, 2/25/04, we had a toxic gas alarm which caused an evacuation of the fab for an hour. The root cause was a weld joint leak in a vacuum pump exhaust line for the LP furnaces. A tiny amount (60ppb) of spent gas was detected at furnace bank 2. The exhaust line was sealed off. There was some confusion concerning if the building should have been evacuated. Allow me to try to refresh your memory. If a toxic gas is detected in a controlled enclosure (i.e. furnace source cabinets, EPI cabinet or the outside gas vaults), then local area is evacuated and the building would not need to be evacuated. For control purposes, the entire fab is considered to be one large room. If a toxic gas is detected in the breathing air of the fab, then the alarms in both the lab and the building are activated and the lab and building must be evacuated. For more information please see below Thanks, Dick >From the SNF safety manual (http://snf.stanford.edu/Labmembers/ManualPartII.pdf ) 10.2 Toxic Gas Alarms Appearance and location of the alarm beacons: The toxic gas alarm beacons are located in the lab and throughout (both inside and outside) the CIS/CISX building. The beacon is a large, flat, round, blue lamp. Alarm conditions and action to be taken: In an alarm condition, the beacon flashes and a very loud klaxon sounds. There are two levels of alarms. In a Level 1 alarm condition, the toxic gas problem is isolated to a gas enclosure. In this case, only the alarm inside the lab will be activated. The lab must be evacuated immediately, but the building need not be. Toxic gases in the lab will be shut off automatically. In a Level 2 alarm condition, the toxic gas problem might not be isolated in an enclosed area. In this case, the alarm beacons throughout the building will be activated. The lab as well as CIS and CISX must be evacuated to the designated assembly point. Toxic gases in the lab will be shut off and the Palo Alto Fire Department will be called, automatically.