Chi On Chui's Oral

Chi On Chui chion at stanford.edu
Mon Jul 26 13:10:22 PDT 2004


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		  University Ph.D. Oral Examination

 Advanced Germanium CMOS Technologies with Nanoscale Dielectrics and
			 Shallow Junctions

			    Chi On Chui
		        (chion at stanford.edu)

		Department of Electrical Engineering
			Stanford University

			 CIS-X  Auditorium

		       Monday, August 2, 2004
			 3:00 pm - 4:00 pm
		   (Refreshments served at 2:45 pm)



	The saturation of silicon MOSFET drain current during traditional
scaling may limit the prospect of future additional scaling required to
continue on the path of Moore's Law.  The lower effective mass and valley
degeneracy of germanium (Ge) could alleviate the problem by providing a
higher source injection velocity.  However, the unstable native oxide for
gate insulation and field isolation, coupled with fast n-type dopant
diffusion for source/drain junction formation are the two classic problems
that have obstructed CMOS device realization in Ge for four decades.

	In this talk, various nanoscale MOS gate dielectrics on Ge are
presented.  The scalability and stability of native Ge oxynitrides will be
examined followed by a seminal investigation and demonstration of
integrating the more scalable and stable high-permittivity metal oxides
for Ge MOS applications.  The effects of different Ge surface cleaning and
passivation strategies will be discussed as well.  In addition, the
activation and diffusion of various p-type and n-type dopants in Ge have
been studied in order to fabricate shallow junctions.  In doing so, two
doping techniques were employed: ion implantation and solid source
diffusion.  Thermal stability on the activated dopants was monitored and
deactivation was observed for the first time.

	Furthermore, two low thermal budget Ge MOSFET fabrication
processes were developed using the above dielectric and junction
technologies.  The first one is a sub-400 ºC p-MOSFET process
incorporating metal gate electrode and high-permittivity dielectrics,
exhibiting p-MOSFETs with enhanced hole mobility.  The second one is a
simple and innovative self-aligned gate-last fabrication process, which
does not only enable functional MOSFETs, but also acts as a vehicle to
evaluate integration of many novel materials.  With further development,
these advanced technologies should allow fabrication of high performance
deep sub-micron Ge MOSFETs required beyond the 32 nm technology node.

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