From guerra at par.stanford.edu Mon Mar 1 14:28:42 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Mon, 1 Mar 2004 14:28:42 -0800 (PST) Subject: Invitation to Sotirios Limotyrakis' Ph.D. Oral Defense Message-ID: Special University Oral Examination POWER-EFFICIENT BROADBAND A/D CONVERSION ------------------------------------------ By SOTIRIOS LIMOTYRAKIS 2:00 pm, Wednesday, 3rd March 2004 CIS Extension Auditorium (Refreshments at 1:45 pm) ABSTRACT Transceivers for modern wireless and wireline communications systems typically include fast, low-power, low-voltage, A/D converters realized in deep-submicron CMOS. For example, the 1000BASE-T Ethernet protocol requires the use of converters with a bandwidth of 60MHz and a resolution of 7 to 9 bits. Similarly, receiver architectures for wireless standards such as the IEEE 802.11a/g also use such high-speed, medium-resolution ADCs. In both cases, low power consumption is a key performance metric. Previously reported stand-alone Nyquist ADCs operating at a rate of 125 MSamples/sec with a resolution of 8 bits typically dissipate more than 100mW of power. This talk introduces a low-power A/D converter suitable for high bandwidth communications applications. The front-end track-and-hold circuit of the converter is followed by a 2.8-bit pipeline stage that comprises two time-interleaved residue generation paths. Two 1.5-bit pipeline stages, implemented using switched-capacitor circuits, follow for each of the residue paths. After digital error correction, each path alternately contributes the 4 most significant bits of the conversion. Each of the two interleaved residue paths concludes with a "backend" A/D converter that encodes the 4 least significant bits and employs a simple folding technique to reduce the number of comparators required. Highlights of the presentation include the design of the front-end track-and-hold circuit and signal scaling that is used to reduce the full scale range of the residue of the first pipeline stage. The signal scaling facilitates the design of a high-speed, high gain operational amplifier with very low power dissipation. An experimental prototype has been integrated in a 0.18um CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150MSamples/sec, it achieves a peak SNDR of 45.4dB for an input frequency of 80MHz. The power dissipation is 71mW. From dwshin at stanford.edu Mon Mar 1 18:54:45 2004 From: dwshin at stanford.edu (Dong-Woon Shin) Date: Mon, 1 Mar 2004 18:54:45 -0800 Subject: Any Buehler's Minimet tools on campus? Message-ID: <1078196085.4043f7758cf8c@webmail.stanford.edu> Dear members I am currently looking for a CMP polisher with constant load. Is there any Buehler's Minimet 1000 or equivalent machine available on campus? (or any place I can have a reasonable access?) Thank you. Sincerely, Dongwoon Shin From mahnaz at snf.stanford.edu Tue Mar 2 09:55:31 2004 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Tue, 02 Mar 2004 09:55:31 -0800 Subject: Litho Update Message-ID: <4044CA93.3B0AEC34@snf.stanford.edu> Hello all, We have made some minor changes to "yes" oven, now if the oven does not reach the set point pressure, the system will alarm. You will need to reset the system and take appropriate steps . All of the steps are written and a copy of the new procedure is next to the system. Please take a few minutes and read it and ask question if any. On Monday 3/1 I found the hot plate 115 tampered with and was at 150 degree, This has happened twice since January of this year. This time the kind labmember wiped out our setting and even put a new mark on the hot plate. What I do not understand is why some one will do such a thing?? There are two other hot plates available, why change the one we all relay on for a specific temperature ( 115)? I need a explanation, am I missing something? We have cleaned both hot plates and if this happens again I will simply pull 115 C hot plate out. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From shott at snf.stanford.edu Wed Mar 3 06:24:23 2004 From: shott at snf.stanford.edu (John Shott) Date: Wed, 3 Mar 2004 06:24:23 -0800 Subject: New virus/hoax warning ... Message-ID: SNF Lab Members: There seems to be a virus/hoax circulating that, at first glance, appears to be coming from a legitimate sender or mailing list. If you receive one of these suspicious messages, you should definitely NOT open the attachment that it claims will protect you. A typical message might look like: Your e-mail account has been temporary disabled because of unauthorized access. For more information see the attached file. Attached file protected with the password for security reasons. Password is 84877. I've receive messages of this type from two different sources in the last 24-hours: one of them appears to be from a legitimate service organization on campus and the other appears to be from a legitimate non-Stanford technical mailing list to which I subscribe. Please be careful and don't open any attachments with messages of this type. Thanks for your attention, John From kevin.maher at memx.com Wed Mar 3 09:51:31 2004 From: kevin.maher at memx.com (Kevin Maher) Date: Wed, 3 Mar 2004 09:51:31 -0800 Subject: Misplaced Cell Phone Message-ID: Last Friday, 2/27, I lost my cell phone. It is a silver Motorola with Verizon service, phone # 650-400-6838. If you have found it, please contact me. Thank you, Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL: From ratiug at stanford.edu Wed Mar 3 11:49:05 2004 From: ratiug at stanford.edu (Ching-Huang Lu) Date: Wed, 3 Mar 2004 11:49:05 -0800 Subject: Misplaced Cell Phone References: Message-ID: <000b01c40158$962edd20$5da60c80@ratiug> I also lost my cell phone in the lab on 02/22(Sunday), Siliver Motorola with AT&T service, 650-8042810. If you found it , please let me know Thanks Ching-Huang ----- Original Message ----- From: Kevin Maher To: labmembers Sent: Wednesday, March 03, 2004 9:51 AM Subject: Misplaced Cell Phone Last Friday, 2/27, I lost my cell phone. It is a silver Motorola with Verizon service, phone # 650-400-6838. If you have found it, please contact me. Thank you, Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL: From vigneshg at stanford.edu Wed Mar 3 22:05:39 2004 From: vigneshg at stanford.edu (Vignesh G Shankar) Date: Wed, 03 Mar 2004 22:05:39 -0800 Subject: Oxidizing Si --> SiO2, dissolving Si Message-ID: <5.2.1.1.2.20040303220119.027efdf8@vigneshg.pobox.stanford.edu> Hi all, These may be obvious questions... but I do not know much about it, so I would appreciate some input. I have a nanostructure (nanopillars) in Si and I wish to convert this to SiO2, without destroying the structure. Any suggestions? Also, I know that HF dissolves silica. Is there a good solvent for Si? Thanks, Vignesh From rcrane at snf.stanford.edu Mon Mar 8 15:44:26 2004 From: rcrane at snf.stanford.edu (Dick Crane) Date: Mon, 08 Mar 2004 15:44:26 -0800 Subject: wbdiff off line 3.8.04 Message-ID: <404D055A.7CDF315A@snf.stanford.edu> Lab members, Just a kind reminder that wbdiff will not be available for use tomorrow, Tuesday, March 9, from 0600 through 1300. The single STi SRD will be replaced by a dual stack handling both 6" and 4". Sorry for inconvenience, but this is another step toward 6" processing capability, Dick From grupp at snowmass.Stanford.EDU Tue Mar 9 15:51:44 2004 From: grupp at snowmass.Stanford.EDU (Dan Grupp) Date: Tue, 9 Mar 2004 15:51:44 -0800 (PST) Subject: high dose implant resist process? Message-ID: Hello, I am having trouble with a 1E15 175 keV implant. the 1 um 3612 resist blisters. Bake must not be long enough. does anyone have a working process for this? Much Thanks, Dan --------------------------------------------------------------------------- Dr. Daniel Grupp Center for Integrated Systems Stanford University Stanford, CA 94305 (650) 724-6911 FAX: 723-4659 --------------------------------------------------------------------------- From guerra at par.stanford.edu Tue Mar 9 16:30:07 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Tue, 9 Mar 2004 16:30:07 -0800 (PST) Subject: Special Seminar: IBM High Speed Circuits Message-ID: SPECIAL SEMINAR "High Speed Circuits in SiGe and CMOS: From mm-wave to Backplane" IBM Dr. Scott K Reynolds (Research Staff Member, PhD, Stanford University) Dr. Mehmet Soyuer (Senior Manager, Research Staff Member, PhD, UC Berkeley) Monday, March 15, 2004 10:00-11:30 a.m. CIS-101 Stanford University ABSTRACT Advances in high speed circuit design, execution, and underlying technology will be critical to meeting the communications requirements of future wireless, wired data communication, and backplane applications. In the wireless arena, the recent development of advanced SiGe transistors with fT and fmax values exceeding 200 GHz may enable low cost implementation of very high data rate wireless communications systems operating in the 60 GHz band, as well as low cost automotive radar systems operating in the 77 GHz band. At lower frequencies, such as in 2.4 or 5 GHz bands, CMOS as well as SiGe are vying for market share while meeting stringent cellular and WLAN system requirements. For future wired data communications systems, techniques enabling the achievement of higher data rates will be of extreme importance. Finally, in the backplane environment, advanced digital CMOS technology must be applied to increasingly challenging analog problems to achieve ever-higher data rates while meeting strict power budgets. In this talk, high speed circuit design work in the Communication Technology department of IBM Research will be described, focusing on four main areas, namely, mm-wave wireless, comparison of W-CDMA RFIC designs in CMOS and SiGe, ultra-high speed serial data communication, and backplane I/O. In each area, the key high-level design goals and challenges will be presented, followed by presentation of circuit design and hardware results for critical sub-blocks. From shott at snf.stanford.edu Tue Mar 9 17:09:26 2004 From: shott at snf.stanford.edu (John Shott) Date: Tue, 9 Mar 2004 17:09:26 -0800 Subject: high dose implant resist process? In-Reply-To: Message-ID: Dan: There are probably a couple of things to try: 1. In the old days, we used to use about 15 minutes under the UV PROM eraser followed by a 30 minute bake at 150 degrees C. While this often gives you some rather nasty looking reticulation in your resist layers, we used to use it when we were masking 5E15 80 keV arsenic source/drain implants. 2. You can also, I think, achieve much the same surface treatment that the UV exposure provides with an appropriate CF4 plasma treatment. Again, I'm foggy on details, but I think that we used to use a couple of minutes in CF4 in drytek 2 followed by a high-temperature bake for about 30 minutes. Jim McVittie can likely speak more authoritatively than I as to whether we can diplicate that type of process today. 3. We also have a not-quite-installed Fusion Deep UV system that is, supposedly, going to provide "one stop shopping" for this type of resist-hardening process ... That machine came to us configured to process 6" wafers and, to be honest, I don't know what is involved in processing smaller wafers. I'm also don't have current information as to when that machine might be available. In the past, we used to have an old BiCMOS run sheet posted on our Web site ... if that is still on there, it should provide some of the details that I've forgotten. Of couse, once you get the resist super hardened in order to with stand that implant ... which, ironically, will harden it still further ... it is often a challenge to get the resist off. We used to use multiple steps alternating between Pirahna and the Matrix. Good luck, John -----Original Message----- From: Dan Grupp [mailto:grupp at snowmass.Stanford.EDU] Sent: Tuesday, March 09, 2004 3:52 PM To: labmembers at snf.stanford.edu Subject: high dose implant resist process? Hello, I am having trouble with a 1E15 175 keV implant. the 1 um 3612 resist blisters. Bake must not be long enough. does anyone have a working process for this? Much Thanks, Dan --------------------------------------------------------------------------- Dr. Daniel Grupp Center for Integrated Systems Stanford University Stanford, CA 94305 (650) 724-6911 FAX: 723-4659 --------------------------------------------------------------------------- From guerra at par.stanford.edu Fri Mar 12 14:25:15 2004 From: guerra at par.stanford.edu (Ann Guerra) Date: Fri, 12 Mar 2004 14:25:15 -0800 (PST) Subject: Reminder Special Seminar: IBM High Speed Circuits In-Reply-To: Message-ID: > > SPECIAL SEMINAR > > "High Speed Circuits in SiGe and CMOS: From mm-wave to Backplane" > > IBM > > Dr. Scott K Reynolds (Research Staff Member, PhD, Stanford University) > Dr. Mehmet Soyuer (Senior Manager, Research Staff Member, PhD, UC > Berkeley) > > Monday, March 15, 2004 > 10:00-11:30 a.m. > CIS-101 > Stanford University > > > ABSTRACT > > Advances in high speed circuit design, execution, and underlying > technology will be critical to meeting the communications requirements of > future wireless, wired data communication, and backplane applications. In > the wireless arena, the recent development of advanced SiGe transistors > with fT and fmax values exceeding 200 GHz may enable low cost > implementation of very high data rate wireless communications systems > operating in the 60 GHz band, as well as low cost automotive radar systems > operating in the 77 GHz band. At lower frequencies, such as in 2.4 or 5 > GHz bands, CMOS as well as SiGe are vying for market share while meeting > stringent cellular and WLAN system requirements. For future wired data > communications systems, techniques enabling the achievement of higher data > rates will be of extreme importance. Finally, in the backplane > environment, advanced digital CMOS technology must be applied to > increasingly challenging analog problems to achieve ever-higher data rates > while meeting strict power budgets. In this talk, high speed circuit > design work in the Communication Technology department of IBM Research > will be described, focusing on four main areas, namely, mm-wave wireless, > comparison of W-CDMA RFIC designs in CMOS and SiGe, ultra-high speed > serial data communication, and backplane I/O. In each area, the key > high-level design goals and challenges will be presented, followed by > presentation of circuit design and hardware results for critical > sub-blocks. > > > From atalasaz at stanford.edu Sun Mar 14 17:56:09 2004 From: atalasaz at stanford.edu (Amir Ali Haj Hossein Talasaz) Date: Sun, 14 Mar 2004 17:56:09 -0800 Subject: Lost wafer boxes Message-ID: <1079315769.40550d394d1e6@webmail.stanford.edu> Dear all, Last Friday in the afternoon, I put some sealed wafer boxes out of the fab near the E-beam lab. Then I went inside e-beam lab. When I came out, I couldn't find the wafer boxes. Any kind of news about those is highly appreciated. Thanks, -Amir From chion at stanford.edu Tue Mar 16 11:42:15 2004 From: chion at stanford.edu (Chi On Chui) Date: Tue, 16 Mar 2004 11:42:15 -0800 (PST) Subject: Unattended opened furnaces and wafers Message-ID: Hi labmembers, The FGA furnace has been left opened with a wafer sitting horizontally on a boat for 30 mins already. /Chi On From rcrane at snf.stanford.edu Fri Mar 19 08:25:28 2004 From: rcrane at snf.stanford.edu (Dick Crane) Date: Fri, 19 Mar 2004 08:25:28 -0800 Subject: Humidity control alert Message-ID: <405B1EF8.7D3FE019@snf.stanford.edu> Lab users, Our ability to control humidity in the litho area will be compromised starting March 22 and continue to be a possible problem for the next four weeks. If we have high humidity days, then the humidity in the litho area could rise above the 45% set point level. This loss of control may disrupt some photoresist processes. We will have normal humidity control in litho through 0600 on March 22 and marginal control thereafter. Why is this happening? Cardinal CoGen, who operates the 60MW cogen plant for Stanford, is doing a major cooling tower upgrade. The CIS building is the only external user of the cooling tower. While the cogen plant has built in redundancies for its steam/electric circuits, CIS, as a parasitic load, operates only on one cooling tower and hence, has no back up. Why did we not know of the shutdown earlier? Our building services such as heating and cooling are provided by Facilities and Operations (FacOps). Although the shutdown has been schedule well in advance, FacOps wasn't notified until a few days ago. What are we going to do? FacOps will attempt to maintain control by creative measures with the air conditioning units. This should work unless the outside humidity is too high. I will be working with FacOps to obtain a portable chiller/heat exchange to be placed in the receiving area to supply the dehumidifier circuit. Shutting down the dehumidifier without backup plans is simply unacceptable. I keep you post as to progress made and I'm sorry for the inconvenience, Dick From rcrane at snf.stanford.edu Fri Mar 19 10:38:36 2004 From: rcrane at snf.stanford.edu (Dick Crane) Date: Fri, 19 Mar 2004 10:38:36 -0800 Subject: STS etcher installation Message-ID: <405B3E2C.3D00B180@snf.stanford.edu> Lab users, There will be minor disruptions in the L109 aisle (Drytek4, STSetch, EPI, and STSetch2) area during the weeks of March 22 and March 29 while the new STSetch2 tool is being installed. Aside from two outside workers occupying the aisle space and a brief interruption (15 min) of STSetch operation, the work should pose only a minor inconvenience. Etch community: Good news, the building permits for the new STSetch2 (HRM) tool have arrived. Permitted work will start Monday, March 22 and should be completed by Friday, April 2. STS will have their installation engineer on site Monday, April 5 through Friday April 16. From Monday, April 19 through Friday April 30, basic process qualifying will be done by J. McVittie and STS. Process transfer may require additional time. Please see J. McVittie for information concerning process development and transfer. Thanks, Dick From kcrozier at stanford.edu Fri Mar 19 14:02:09 2004 From: kcrozier at stanford.edu (Kenneth Brian Crozier) Date: Fri, 19 Mar 2004 14:02:09 -0800 Subject: multilayered SOI wafers ? Message-ID: <5.2.0.9.2.20040319135839.02a0d738@kcrozier.pobox.stanford.edu> Hello everyone, I would greatly appreciate it if you could drop me a line if you have purchased or made multilayered SOI wafers. We would like to have SOI wafers with a 0.5 um thick Si top layer, followed by 1um oxide, followed by 0.5 um Si, followed by 1 um oxide and then the bulk Si. thanks very much, Ken --------------------------------------------- Ken Crozier, Ph.D. room GL 51, Ginzton Laboratory, Stanford University, Stanford, CA 94305, USA tel : 650-723-1945 fax : 650-725-2533 From marklee at icsl.ucla.edu Fri Mar 19 14:48:55 2004 From: marklee at icsl.ucla.edu (Mark Lee) Date: Fri, 19 Mar 2004 14:48:55 -0800 Subject: multilayered SOI wafers ? References: <5.2.0.9.2.20040319135839.02a0d738@kcrozier.pobox.stanford.edu> Message-ID: <003c01c40e04$61d762a0$815b6180@polaris> Hi, dear member and Ken I am also interested in double SOI wafer. sincerely, Mark ----- Original Message ----- From: "Kenneth Brian Crozier" To: Sent: Friday, March 19, 2004 2:02 PM Subject: multilayered SOI wafers ? > > > Hello everyone, > > I would greatly appreciate it if you could drop me a line if you have > purchased or made multilayered SOI wafers. > > We would like to have SOI wafers with a 0.5 um thick Si top layer, followed > by 1um oxide, followed by 0.5 um Si, followed by 1 um oxide and then the > bulk Si. > > thanks very much, > Ken > --------------------------------------------- > Ken Crozier, Ph.D. > room GL 51, Ginzton Laboratory, > Stanford University, Stanford, CA 94305, USA > tel : 650-723-1945 fax : 650-725-2533 > From mprao at engineering.ucsb.edu Fri Mar 19 15:53:36 2004 From: mprao at engineering.ucsb.edu (Masa Rao) Date: Fri, 19 Mar 2004 15:53:36 -0800 Subject: multilayered SOI wafers ? References: <5.2.0.9.2.20040319135839.02a0d738@kcrozier.pobox.stanford.edu> <003c01c40e04$61d762a0$815b6180@polaris> Message-ID: <013d01c40e0d$64ee0260$5d486f80@mee.ucsb.edu> Check out Ultrasil.com. They have a surplus SOI inventory list on their website that's updated weekly and they also will do small run custom orders, even double SOI for a reasonable price. Masa ----- Original Message ----- From: "Mark Lee" To: ; "Kenneth Brian Crozier" Sent: Friday, March 19, 2004 2:48 PM Subject: Re: multilayered SOI wafers ? > Hi, dear member and Ken > > I am also interested in double SOI wafer. > > sincerely, > > Mark > ----- Original Message ----- > From: "Kenneth Brian Crozier" > To: > Sent: Friday, March 19, 2004 2:02 PM > Subject: multilayered SOI wafers ? > > > > > > > > Hello everyone, > > > > I would greatly appreciate it if you could drop me a line if you have > > purchased or made multilayered SOI wafers. > > > > We would like to have SOI wafers with a 0.5 um thick Si top layer, > followed > > by 1um oxide, followed by 0.5 um Si, followed by 1 um oxide and then the > > bulk Si. > > > > thanks very much, > > Ken > > --------------------------------------------- > > Ken Crozier, Ph.D. > > room GL 51, Ginzton Laboratory, > > Stanford University, Stanford, CA 94305, USA > > tel : 650-723-1945 fax : 650-725-2533 > > > > > From mtang at snf.stanford.edu Fri Mar 19 17:18:02 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Fri, 19 Mar 2004 17:18:02 -0800 Subject: ME342-AB MEMS Lab Course Announcement Message-ID: <405B9BCA.144FF741@snf.stanford.edu> Hi everyone -- Here's a course announcement from Prof. Pruitt: ME342-AB MEMS Laboratory, 4 units lecture: Tuesday/Thursday 2:15-4:05 labs: days to be assigned, 8am-12:30pm This new course focused on the fabrication and project based design, analysis, and testing of MEMS sensors will be offered in Spring and Summer quarters. The first quarter of this two part sequence utilizes the Stanford Nanofabrication Facility for the laboratory sessions to fabricate piezoresistive force sensors using a predesigned process. The sensors will be analyzed, tested, and calibrated. Lectures will survey associated topics in MEMS. The second quarter provides team based design projects with defined challenges and applications. The outcomes of the second quarter should be suitable for conference publications. Enrollment is limited but multidisciplinary teams are encouraged. If you are interested, please visit http://www.stanford.edu/class/me342/class_info.html to download and complete a questionnaire to be turned in at the first day of class, Tuesday March 30. Course participants and waitlist will be posted later that evening. Please check the website or Axess for updated room location information, we are looking for a larger venue at least for the first lecture. Hope to see you on the first day! Beth Pruitt Assistant Professor Mechanical Engineering pruitt at stanford.edu -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at snf.stanford.edu Tue Mar 23 10:32:17 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Tue, 23 Mar 2004 10:32:17 -0800 Subject: SNF/Nanocharacterization Lab Open House Message-ID: <406082B1.3F8507D9@snf.stanford.edu> Announcing: The First SNF/Nanocharacterization Lab Open House Time/Date: 9 am ? 5 pm, Tues-Wed, April 20-21, 2004 Location: CIS and GLAM buildings More info: http://snf.stanford.edu/Labmembers/OpenHouse.html This year, SNF joins 12 other University facilities in the NSF-sponsored National Nanotechnology Infrastructure Network (the NNIN). This not only ensures us stable infrastructure support, but also adds new capabilities to be made available to our labmembers through the expanded network. (For more information about the NNIN, check out the links on the SNF home page.) The expansion at Stanford features the new Nanocharacterization Laboratory in GLAM and K-12 Educational Outreach programs. This Open House is in celebration of the NNIN; it's also an opportunity to learn about these new capabilities and a chance to check out what your fellow labmembers are up to. This is a community event, so participation at ALL levels are welcome. Some of the activities planned: 1. Poster session -- We welcome posters from all labmembers. If you've got a poster from a previous conference or meeting, by all means, share it with your fellow labmembers. Free SNF T-shirts to poster presenters. 2. Technical Presentations ? (20 min to 50 min each) - Research seminars: Labmembers and PI?s are invited to present. Here?s a chance to share what you?ve done (or what you?re doing), and maybe even get some feedback from your fellow labmembers. - Tutorials: Staff from SNF and the Nanocharacterization Laboratory will be offering tutorials on processes, methods, and other useful tips and tricks ranging from the basic to advanced levels. Labmembers wishing to share expertise on any lab-related topic are welcome to present a tutorial. - Product presentations: We have invited several of our trusted vendors to give technical presentations. If you would like to see a specific topic or product, send your suggestions. 3. Mini-Trade Show -- There will be opportunities for labmembers to meet vendors in the mini-trade show. If you are an equipment, materials, or service provider interested in sponsoring a table for a nominal fee, let us know. Labmembers: if you?d like to suggest a vendor, let us know ? we hope that everyone will use this as a chance for labmembers to learn about commercial resources and for vendors to learn what our researchers want to see. So mark your calendars! Tell your friends! The first SNF/Nanocharacterization Lab Open House is coming soon! -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mike.daneman at arrayedfiberoptics.com Mon Mar 22 15:26:02 2004 From: mike.daneman at arrayedfiberoptics.com (Mike Daneman) Date: Mon, 22 Mar 2004 15:26:02 -0800 Subject: UV dicing tape In-Reply-To: <405B9BCA.144FF741@snf.stanford.edu> Message-ID: Hello, I'm trying to buy some UV-releasable dicing tape, however it is only available in huge 100m rolls for ~$300. Since it has a limited shelf life (6 months - 1 year) and I will never use it all in that time, I was wondering if anyone is interested in either of the following two options: 1. Splitting the cost of the roll among multiple people (preferably more than 2). or 2. If anyone has recently bought a roll and is willing to sell part of it to me. Thanks, -Mike. From rosanna at snf.stanford.edu Wed Mar 24 16:30:15 2004 From: rosanna at snf.stanford.edu (Rosanna Dohm) Date: Wed, 24 Mar 2004 16:30:15 -0800 Subject: SPECIAL SEMINAR 4/1/04 Message-ID: SPECIAL SEMINAR Thursday, 4/1/04 3:00 p.m. CIS-101 "Nanoscale Nonvolatile Memory Technology and its Application to Molecular Interface" Edwin Chihchuan Kan School of Electrical and Computer Engineering Cornell University ABSTRACT Nonvolatile memory based on confined charges has seen the largest market growth in the last decade. However, the cost, storage density and high-voltage operations has posed severe limitation to its pervasive and ubiquitous applications. The key to high density, low voltage, fast writing and ultra-high endurance lies in the use of direct tunneling oxide while still keeping the retention time up to 3-10 years. From the physical principles, the metal nanocrystal memory is superior to the other discrete storage options such as SONOS and Si/Ge nanocrystal memories. This talk will present the experimental characterization of the operations and reliability of metal nanocrystal memories. Static charge in the nonvolatile memory can also be perceived as a convenient and low-power interface to the world outside of CMOS electronics. We will demonstrate the operating principles for modified surface electrochemistry from static charge injection for molecular sensing and actuation, and establish arguments why this is an effective approach over the conventional electrode and cantilever-based methods. We will also discuss what is the necessary technology development to bring forth a programmable biochemical end that can eventually serve as a universal detector and actuator in the microbiological level. BIOGRAPHY Edwin Chihchuan Kan received his B.S. degree from National Taiwan University, Taipei,Taiwan, R.O.C., in 1984, and the M.S. and Ph.D. degrees from the University of Illinois,Urbana-Champaign, in 1988 and 1992, respectively, all in electrical engineering. From 1984 to 1986, he served as a Second Lieutenant in the Air Force, Taiwan, R.O.C. In 1992,he joined Dawn Technologies as a Principal CAD Engineer developing advanced electronic and optical device simulators and technology CAD framework. He was then with Stanford University, as a Research Associate from 1994 to 1997 under the supervision of Prof. R. W. Dutton. From 1997 to 2002, he was an Assistant Professor with the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, where he is now an Associate Professor. He spent the summers of 2000 and 2001 at IBM Microelectronics, Yorktown Heights and Fishkill, NY, in the IBM Faculty Partner Program. His main research areas include CMOS technology, semiconductor device physics, integrated autonomous systems, and technology CAD. Dr. Kan received the Presidential Early Career Award for Scientists and Engineer (PECASE) in October 2000 from the White House of the US Federal Government. He also received several teaching awards from Cornell Engineering College for his CMOS and MEMS courses. He plans to spend his coming sabbatical year in Intel and Stanford between July 2004 and July 2005. From dshankar at stanford.edu Fri Mar 26 11:06:42 2004 From: dshankar at stanford.edu (Shankar Devasenathipathy) Date: Fri, 26 Mar 2004 11:06:42 -0800 Subject: mold release Message-ID: <1080328002.40647f4232eeb@webmail.stanford.edu> All, I am looking for a mold release to allow easy removal of PDMS from the stamp. Would like to check with users on whether Glassclad 6C would be applicable, and on possible alternatives. Thanks, Shankar. From shott at snf.stanford.edu Sun Mar 28 11:48:16 2004 From: shott at snf.stanford.edu (John Shott) Date: Sun, 28 Mar 2004 11:48:16 -0800 Subject: Star Office 7 ... Message-ID: SNF Lab Members: Several of you have pointed out that the previous version of Star Office was broken in that it reported an expired licence. We have now downloaded and installed the latest version of Star Office (version 7) that should be a permanent installation that will not expire. You will find that there is a Star Office icon at the left end of the task bar (at the bottom of your screen) that can be used to start up Star Office. The first time that you do this, it will take you through a short (~5 minute) installation sequence. There are only two things to watch out for: 1. At one point, it will ask you whether you want to perform a Workstation Install (that, I think, consumes only 1.5 MB of disk space) or a Local Install (that consumes something like 360 MB of space). Please choose the Workstation (1.5 MB) option. There are no advantages to the Local Install option ... and we will remove any full installs of this type without asking ahead of time. 2. Near the end, it will warn you about not having installed the Adabas database ... we do not have nor will we support this database so please ignore this warning. Please let me know if you have any problems installing or using Star Office. If you are unfamiliar with Star Office, it is based on Open Office that is an open source software package that behaves much like Microsoft Word and Excel ... but runs on virtually all platforms and operating systems. In particular, it is capable of reading and writing both *.doc and *.xls files that may be transferred from/to Windows platforms. Thanks for your continued support, John -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Tue Mar 30 11:45:21 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Tue, 30 Mar 2004 11:45:21 -0800 Subject: ME342 Message-ID: <4069CE51.FEA1CB3E@snf.stanford.edu> Labmembers -- Just when you thought the rush of new students in the lab was over with EE410 ending for the term... now there's ME342! The lab portion of this class commences next week. Students will be working in groups under an experienced TA from about 8:30-12:30, Mondays through Thursdays, through early May. If you'd like to plan around their schedule, check out the syllabus at: http://www.stanford.edu/class/me342/handouts.html This class will be slightly different from EE410 in that the students will receive a lot more hands-on experience with equipment and will be using the lab outside these normal class hours. Please be patient with them and help indoctrinate them into the SNF culture, where you can (now's your chance -- in a few short weeks, these students will be your fellow labmembers!) And of course, please direct them to the nearest staff member for help when needed. Thanks for your attention -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mwiemer at stanford.edu Tue Mar 30 15:07:45 2004 From: mwiemer at stanford.edu (Michael Wiemer) Date: Tue, 30 Mar 2004 15:07:45 -0800 Subject: Zinc Deposition References: <4069CE51.FEA1CB3E@snf.stanford.edu> Message-ID: <003101c416ab$d02a2c60$766140ab@longmorn> Labmembers, I am interested in depositing a Zinc - Gold contact on P-type GaAs. Zinc has a very low vapor pressure and so needs a dedicated system which is why we can't do this at SNF. Do any of you know of any companies or places where I might be able to deposit Zinc (or a Gold-Zinc alloy?). Thanks, -Mike