high dose implant resist process?

John Shott shott at snf.stanford.edu
Tue Mar 9 17:09:26 PST 2004


There are probably a couple of things to try:

1. In the old days, we used to use about 15 minutes under the UV PROM eraser
followed by a 30 minute bake at 150 degrees C.  While this often gives you
some rather nasty looking reticulation in your resist layers, we used to use
it when we were masking 5E15 80 keV arsenic source/drain implants.

2. You can also, I think, achieve much the same surface treatment that the
UV exposure provides with an appropriate CF4 plasma treatment.  Again, I'm
foggy on details, but I think that we used to use a couple of minutes in CF4
in drytek 2 followed by a high-temperature bake for about 30 minutes.  Jim
McVittie can likely speak more authoritatively than I as to whether we can
diplicate that type of process today.

3. We also have a not-quite-installed Fusion Deep UV system that is,
supposedly, going to provide "one stop shopping" for this type of
resist-hardening process ... That machine came to us configured to process
6" wafers and, to be honest, I don't know what is involved in processing
smaller wafers.  I'm also don't have current information as to when that
machine might be available.

In the past, we used to have an old BiCMOS run sheet posted on our Web site
... if that is still on there, it should provide some of the details that
I've forgotten.

Of couse, once you get the resist super hardened in order to with stand that
implant ... which, ironically, will harden it still further ... it is often
a challenge to get the resist off.  We used to use multiple steps
alternating between Pirahna and the Matrix.

Good luck,


-----Original Message-----
From: Dan Grupp [mailto:grupp at snowmass.Stanford.EDU] 
Sent: Tuesday, March 09, 2004 3:52 PM
To: labmembers at snf.stanford.edu
Subject: high dose implant resist process?

   I am having trouble with a 1E15 175 keV implant. the 1 um 3612 resist
blisters.  Bake must not be long enough. does anyone have a working process
for this?
Much Thanks,

Dr. Daniel Grupp
Center for Integrated Systems
Stanford University
Stanford, CA 94305
(650) 724-6911
FAX:  723-4659

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