Ph.D. Oral Examination -- Yaocheng Liu (Monday, December 6, 2004, 9:30AM)

Yaocheng Liu ychliu at
Mon Nov 29 11:39:02 PST 2004

Silicon and Germanium Crystallization Techniques for Advanced Device Applications


University Oral Examination

Yaocheng Liu

Department of Materials Science and Engineering, Stanford University


Monday, December 6, 2004, 9:30AM (Refreshments will be served at 9:15AM)

Cypress Auditorium, Paul Allen Center for Integrated Systems (CIS-X 101)


Tremendous challenges exist as semiconductor devices are scaled down to the nanometer regime.  New materials and novel devices are introduced to solve various problems.  Three-dimensional integrated circuits are believed to be one of the approaches to reduce the interconnect delay.  Metal-induced crystallization (MIC) of amorphous Si is of interest because it can produce high-quality Si crystals with low-temperature processing, enabling the monolithic integration of multilevel devices and circuits.  A two-step MIC process was developed to make single-crystal Si pillars on insulator by forming a NiSi2 template in the first step and crystallizing the amorphous Si by NiSi2-mediated solid-phase epitaxy (SPE) in the second step.  TEM study clearly showed the quality improvement over the traditional MIC process.  This part of work will be covered briefly.

The rest of the presentation will focus on the fabrication of Ge-on-insulator (GeOI) substrates and devices.  Ge is of interest due to its high carrier mobility and excellent optoelectronic properties.  GeOI is desired to achieve high device performance and to solve the process problems traditionally associated with bulk Ge wafers.  High-quality Ge crystals and Ge-on-insulator structures were grown on Si substrates using a novel rapid melt growth (RMG) technique that integrates the key elements in CZ growth - seeding, melting, epitaxy and defect necking.  Growth velocity and nucleation rate were calculated to determine the RMG process window.  Self-aligned microcrucibles were created with low-pressure CVD SiO2 to hold the Ge liquid during the RMG annealing.  Material characterization showed a very low defect density for the RMG GeOI structures.  The Ge film was relaxed, with its orientation controlled by the Si substrate.  Ultra-thin film GeOI was obtained.  The RMG process was simple and robust.

P-channel MOSFETs and p-i-n photodetectors were fabricated with the as-prepared GeOI substrates.  The effective hole mobility at 0.4MV/cm effective E-field was estimated to be 120cm2/Vs, which is 20% higher than Si universal mobility at the same electrical field.  Tri-gate MOS transistors were also fabricated using Ge fins on insulator grown by the same RMG technique.  The Ge photodetectors were functional at wavelengths of both 850nm and 1550nm, showing high responsivity and fast impulse response.  These results indicated that the RMG GeOI substrates were well suited for device fabrication.  With the RMG technology, Ge devices can be easily integrated into a Si IC fabrication process.

Finally a new theory, growth-induced barrier lowering (GIBL), is proposed to understand the phenomena corresponding to rapid melt growth and solid-phase epitaxy.  Thermodynamic derivations show that the energy barrier for nucleation is reduced when the growth front impinges on some of the sub-critical embryos, making it possible for the embryos to grow and form defects.  This theory can explain the quality difference between RMG and SPE.  It can also explain why SPE ultra-thin films are often defective while RMG can produce high-quality films with thickness of nanometer scale.
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