EE310 Integrated Circuits Seminar, 10/5/04

Ann Guerra guerra at par.stanford.edu
Mon Oct 4 13:59:46 PDT 2004


"Silicon Devices at the 'End of Scaling' -- Opportunities and Challenges"

		H.-S. Philip Wong
	Dept. of Electrical Engineering
		Stanford University

	     Tuesday, October 5, 2004
		     4:15 p.m.
		    Packard-101

		      ABSTRACT

As silicon CMOS devices scale into the nanometer regime, the material set
and device structures employed by conventional Si FET are beginning to
reach their limits. We begin this talk by outlining the opportunities for
device performance improvements, along with potential challenges and
solutions to the challenges. Examples of research topics of current
interest will be given. These include: transport-enhanced devices,
multi-gate FETs, and other novel devices. Directions for further research
will be discussed.



		     BIOGRAPHY
H.-S. Philip Wong joined the IBM T. J. Watson Research Center, Yorktown
Heights, New York, in 1988. In September, 2004, he joined Stanford
University as Professor of Electrical Engineering.

While at IBM Research, he was a Senior Manager having the responsibility
of shaping and executing IBMs strategy on nanoscale science and technology
and semiconductor technology. At IBM, he performed and managed research
that has a time horizon that rivals the most adventurous university
research.

His research interests are in nanoscale science and technology,
semiconductor technology, solid state devices, and electronic imaging. He
is interested in exploring new materials, novel fabrication techniques,
and novel device concepts for future nanoelectronics systems. Novel
devices often require new concepts in circuit and system designs. His
research also includes explorations into circuits and systems that are
device-driven.
(URL: http://www.stanford.edu/~hspwong).

He is a Fellow of the IEEE. He is a member of the Emerging Research
Devices Working Group of the International Technology Roadmap for
Semiconductors (ITRS).





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