Rohit Shenoy - Ph.D. Oral Examination - Friday Oct 1 2pm
Rohit S. Shenoy
rohits at stanford.edu
Tue Sep 28 00:55:31 PDT 2004
Stanford University Ph.D. Oral Examination
"Technology and Scaling of Ultrathin Body Double-Gate FETs"
Rohit S. Shenoy
Department of Electrical Engineering
Friday, Oct 1, 2004
2:00 pm - 3:00 pm
(Refreshments at 1:45 pm)
As silicon CMOS technology advances into the sub-50 nm regime,
fundamental and manufacturing limits impede the traditional scaling
of transistors. Innovations in materials and device structures will
be needed for continued transistor miniaturization with commensurate
performance improvements. The ultrathin body double-gate (DG) FET is
a leading candidate for replacing bulk CMOS transistors in future
technology generations. Multiple gates and the ultrathin body enable
better electrostatic gate control over the channel, allowing DG FETs
to be scaled to smaller dimensions than their conventional bulk
counterparts. This research is focused on some of the major issues
in the design and fabrication of high performance scaled DG FETs.
The first part of the talk deals with extrinsic factors that limit
the overall performance of ultrathin body DG FETs. The impact of
parasitic capacitance and resistance is studied and quantified by
device simulation. In particular, the importance of optimizing the
lateral doping profile in the thin source/drain extension regions to
minimize series resistance is discussed in detail.
Next, a novel process is proposed to fabricate the ideal planar DG
FET with the following attributes: 1) deposition controlled uniform
ultrathin body, 2) fully self-aligned gates for low parasitic
capacitance, and 3) flared-out low resistance source/drain regions.
Experimental work on the unit process development verifies the
feasibility of the key steps. As proof of concept, functional
transistors with very good turn-off characteristics are demonstrated.
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