From rostam at stanford.edu Fri Apr 1 22:47:55 2005 From: rostam at stanford.edu (Rostam Dinyari) Date: Fri, 1 Apr 2005 22:47:55 -0800 Subject: particle suspension Message-ID: <1112424475.424e401baeb3a@webmail.stanford.edu> Hi, I have a sample of one kind of cell (about 5 micron in diameter) and I'd like to mix them with a suspension of particles of any diameter range between 100nm-10microns. Any particle in this range will work for me and they need not to be something special; I just would like to look at them in a definite machine (FACS). However, the solvent should be something which lets the cells be alive (not acetone or ...). So, I'm wondering if you have any suspension which you don't need or an idea that how I may provide some amount for myself. Thanks, Rostam From mbaran at stanford.edu Mon Apr 4 11:27:09 2005 From: mbaran at stanford.edu (Maureen Baran) Date: Mon, 4 Apr 2005 11:27:09 -0700 Subject: Watch Found in Gowning Room Message-ID: <200504041827.j34IR9tv011469@smtp3.Stanford.EDU> One of our Labmembers has turned in a watch that she found, sometime this morning, in the Gowning Room. If this is your watch please come to cubicle #41 and claim it. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kevhuang at stanford.edu Mon Apr 4 13:31:44 2005 From: kevhuang at stanford.edu (Kevin Huang) Date: Mon, 4 Apr 2005 13:31:44 -0700 Subject: wet etching of SiO2 Message-ID: <1112646704.4251a4307bfde@webmail.stanford.edu> Hi, I would like to release some structure in the device layer of SOI wafers (10 um/ 2 um/ 450 um SOI wafer). The size of the structure will be about 2 mm by 2 mm. And I will etch the oxide on the whole 4" wafer. I read on the website about the etching rate. Even if I use 49% concentrated HF to etch, it will take about 20 hours to etch. My questions are: 1) Is this a reasonable time to be expected when doing the etching? 2) Since the 49% HF is not buffered, will the acid work well for up to 20 hours or do I need to refresh the acid constantly? Thank you for your time. Kevin From mtang at snf.stanford.edu Wed Apr 6 12:54:54 2005 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 06 Apr 2005 12:54:54 -0700 Subject: CAD Room PC's Message-ID: <42543E8E.2070907@snf.stanford.edu> Hi everyone -- Just wanted to let you know that we'll be upgrading the PC's in the CAD room. They won't be state-of-the-art, but they will be better than the ones there now. We'll make every effort to keep the drives with data, or at least, back them up. But it would probably be a very good idea if everyone took the time to backup their personal files themselves as well... just in case... (I've been known to fry a drive in my time...) By the way, the PC's will be updated with the just-released LEdit 11.2. We've also acquired the MEMS license for one of our LEdit keys (allowing import/export to DXF and some non-Manhattan geometry functions.) We've also acquired (with many thanks to Dan Grupp) the Coventor MEMulator which has 3-D visualization functions. These will be installed on one of the upgraded PC's. Thanks for your attention -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From saraswat at cis.stanford.edu Thu Apr 7 10:34:05 2005 From: saraswat at cis.stanford.edu (saraswat) Date: Thu, 7 Apr 2005 10:34:05 -0700 Subject: Your headlights are on Message-ID: If you own a blue Honda Del Sol 5GFR727, you left your headlights on. Krishna ------ From jzheng at rheosense.com Thu Apr 7 11:22:12 2005 From: jzheng at rheosense.com (Jun Zheng) Date: Thu, 7 Apr 2005 11:22:12 -0700 Subject: Black wax for KOH etching Message-ID: <000601c53b9e$bad4d8b0$6901a8c0@RheoSenseJun> Hi, Everyone: I used to see people using black wax for protection during KOH etching at 80C. Does anyone know the vendor and part number of this black wax. If you know more detail, please let me know. Thanks! Jun Zheng Senior MEMS Engineer RheoSense Inc. (925)866-3802 -------------- next part -------------- An HTML attachment was scrubbed... URL: From shott at snf.stanford.edu Thu Apr 7 13:02:24 2005 From: shott at snf.stanford.edu (John Shott) Date: Thu, 07 Apr 2005 13:02:24 -0700 Subject: SNF Lab Open .... Message-ID: <425591D0.5050207@snf.stanford.edu> An HTML attachment was scrubbed... URL: From jerabek at snf.stanford.edu Thu Apr 7 13:56:46 2005 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Thu, 7 Apr 2005 13:56:46 -0700 (PDT) Subject: Black wax for KOH etching In-Reply-To: <000601c53b9e$bad4d8b0$6901a8c0@RheoSenseJun> Message-ID: I have a piece of the black wax you are looking for. If you want it it's all yours. I am in CIS#142. -Paul On Thu, 7 Apr 2005, Jun Zheng wrote: > Hi, Everyone: > > I used to see people using black wax for protection during > KOH etching at 80C. Does anyone know the vendor and part number of this > black wax. If you know more detail, please let me know. > > Thanks! > > Jun Zheng > Senior MEMS Engineer > RheoSense Inc. > (925)866-3802 > > From mbaran at stanford.edu Mon Apr 11 09:05:12 2005 From: mbaran at stanford.edu (Maureen Baran) Date: Mon, 11 Apr 2005 09:05:12 -0700 Subject: Ethernet Card Found Sunday Message-ID: <200504111605.j3BG5Drp032074@smtp1.Stanford.EDU> Good Morning Everyone, An Ethernet Card for a Laptop was found yesterday during Community Day. If this is your card please come by cubicle #41 and let me know who the manufacturer of the card is. Thanks, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Mon Apr 11 10:48:40 2005 From: mtang at snf.stanford.edu (Mary Tang) Date: Mon, 11 Apr 2005 10:48:40 -0700 Subject: Wet Benches/Develop Tracks Down Message-ID: <425AB878.1030202@snf.stanford.edu> Hi everyone -- We're sorry to report that the acid wet benches and developer tracks/benches remain down for the time being. There was a power glitch last night which caused the Acid Waste Neutralization system to dump all its base into the holding tank. So, the AWN is out of commision right now until the service contractor can come in to drain the tank and refill the base. They are due in at any moment now (supposedly, some time this morning), but in the meantime, all stations which use the AWN will remain unavailable for use. We'll send a note out when the AWN system is repaired. The cause of the glitch and ensuing effects are under investigation now. (By the way, many thanks to Eric P, who shutdown the acid and developer stations last night, thereby helping to prevent an overflow situation.) Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From rcrane at snf.stanford.edu Mon Apr 11 16:44:14 2005 From: rcrane at snf.stanford.edu (Dick Crane) Date: Mon, 11 Apr 2005 16:44:14 -0700 Subject: Acid waste neutralizer is back up Message-ID: <425B0BCE.4020304@snf.stanford.edu> Attention fab users, The acid waste neutralizer crisis is now over. The wet benches (and litho developer) are back to normal operations. Thanks for your cooperation and sorry for the inconvenience, Dick From vigneshg at stanford.edu Mon Apr 11 18:17:49 2005 From: vigneshg at stanford.edu (Vignesh G) Date: Mon, 11 Apr 2005 18:17:49 -0700 Subject: Kelvin Probe on campus? Message-ID: <6.2.1.2.2.20050411181005.039e03e8@vigneshg.pobox.stanford.edu> Hi all, I am wondering if any of you have used on campus / have access to in Stanford / know how to make / know where to buy (for cheap) a Kelvin probe. Thanks. - Vignesh. From edwardsj at stanford.edu Mon Apr 11 20:23:41 2005 From: edwardsj at stanford.edu (Jane Edwards) Date: Mon, 11 Apr 2005 20:23:41 -0700 Subject: FW: Stanford Workshop: Probing the Nanoscale-2nd Notice Message-ID: <000201c53f0f$07379670$6501a8c0@AVANDEL> Subject: Workshop: Probing the Nanoscale The Center for Probing the Nanoscale (CPN) An NSF Nanoscale Science & Engineering Center, a Joint Venture of Stanford University and IBM Research Labs First Annual Workshop: Probing the Nanoscale Sunday, May 8, 2005 April 9, 2005 - Second Notice REGISTER ONLINE below You are cordially invited to attend CPN's inaugural event: Probing the Nanoscale, a one-day workshop on challenges and approaches to visualizing nanoscale structures. Hear talks by leading experts from industry and academia. Meet CPN investigators and the broader Bay Area community interested in nanoscale imaging and metrology. Location: Bloch Lecture Hall of the William R. Hewlett Teaching Center, 730 Serra Mall, Science and Engineering Quad at Stanford University. Hours: 8:30-6, with continental breakfast and box lunch included. There will be a poster session from 4-6, during which tasty, light fare will be served. Speakers include: Dr. Storrs Hoen, Agilent Laboratories, "An Approach to High-Speed Atomic Force Microscopy" Professor Olav Solgaard, Stanford Univ. Electrical Engineering Dept, Solid State Photonics Lab, "Time Resolved Measurements of Tip-Sample Interaction Forces in Tapping-Mode AFM" Dr. Susan Holl, Intel, "Metrology Challenges in the Semiconductor Industry" Dr. Michael Mermelstein, Umech, "Trends in Computer-Enabled Optical Microscopy" Professor Davis Baird, Dept. of Philosophy and NanoCenter, University of South Carolina, "On Nano Movies" Linda Chao, Stanford University Office of Technology Licensing, "Technology Licensing at Stanford University" Dr. Steve Minne, Veeco, "Designing for Technology Transfer" Dr. Dieter Weller, Seagate Recording Media Operations, "Metrology Needs in the Magnetic Recording Industry" Register online NOW! Questions: Laraine Lietz-Lucas, lietz at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From goldhaber-gordon at stanford.edu Tue Apr 12 13:28:15 2005 From: goldhaber-gordon at stanford.edu (David Goldhaber-Gordon) Date: Tue, 12 Apr 2005 13:28:15 -0700 Subject: Poster session at Workshop on Probing the Nanoscale. May 8, Stanford. Message-ID: <009901c53f9e$27fd1fd0$6601a8c0@cocoanibs> Dear students and postdocs, Doing something neat in nanotechnology or nanoscience? Using microfabrication to create phenomena which could not occur (or be observed) otherwise? I strongly encourage you to attend the first annual workshop on Probing the Nanoscale here at Stanford, Sunday May 8, and to PRESENT A POSTER. We expect substantial interest in the poster session from Bay Area academic and especially industrial scientists who are eager to meet you and hear about your work. Posters will also be judged for attractive prizes ($500 first prize, two $100 runners-up). In addition to the posters, we have an exciting all-day roster of talks, covering not only techniques for observing nanoscale objects but also connections to major industrial challenges, and how scientists communicate with the public: http://www.stanford.edu/group/cpn/workshop2005/index.html Registration is only $25 for students -- this includes breakfast, lunch, and hors-d'oeuvres during the poster session. When you register, please email Laraine Lietz-Lucas lietz at stanford.edu, Program Manager of the Center for Probing the Nanoscale, to sign up to give a poster. Please do this by April 30 at latest, to ensure we have enough poster boards set up, enough food, etc. Tell your friends and colleagues! Below I copy the announcement of the Workshop. Best wishes, David CPN: Center for Probing the Nanoscale An NSF Nanoscale Science and Engineering Center, a Joint Venture of Stanford University and IBM Research Labs First Annual Workshop Probing the Nanoscale Sunday, May 8, 2005 You are cordially invited to attend the CPN's inaugural event: Probing the Nanoscale, a one-day workshop on challenges and approaches to visualizing nanoscale structures. Hear talks by leading experts from industry and academia. Meet CPN investigators and the broader Bay Area community interested in nanoscale imaging and metrology. Location: Bloch Lecture Hall of the William R. Hewlett Teaching Center (TCSEQ), 730 Serra Mall, Science and Engineering Quad at Stanford University. Hours: 8:30-6, with continental breakfast and box lunch included. There will be a poster session from 4-6, during which tasty, light fare will be served. Speakers include: Dr. Storrs Hoen, Agilent Laboratories "An Approach to High-Speed Atomic Force Microscopy" Professor Olav Solgaard, Stanford Univ. Electrical Engineering Dept, Solid State Photonics Lab "Time Resolved Measurements of Tip-Sample Interaction Forces in Tapping-Mode AFM" Dr. Susan Holl, Intel "Metrology Challenges in the Semiconductor Industry" Dr. Michael Mermelstein, Umech "Trends in Computer-Enabled Optical Microscopy" Professor Davis Baird, Dept. of Philosophy and NanoCenter, University of South Carolina "On Nano Movies" Linda Chao, Stanford University Office of Technology Licensing "Technology Licensing at Stanford University" Dr. Steve Minne, Veeco "Designing for Technology Transfer" Dr. Dieter Weller, Seagate Recording Media Operations "Metrology Needs in the Magnetic Recording Industry" Register online NOW! http://www.stanford.edu/group/cpn/workshop2005/registration.html Questions: Laraine Lietz-Lucas, lietz at stanford.edu ------------------------------------------------------------------------ ---- David Goldhaber-Gordon goldhaber-gordon at stanford.edu Assistant Professor of Physics davidg at post.harvard.edu Deputy Director, Center for Probing the Nanoscale Stanford University (permanent forwarding) www.goldhaber-gordon.com (650) 725-2047 (lab) (650) 724-3709 (office) Address for letters or packages: Administrative Associate: David Goldhaber-Gordon Roberta Edwards Geballe Laboratory for Advanced Materials McCullough, Rm. 338 McCullough Building, Room 346 Phone: (650) 723-8028 476 Lomita Mall Fax: (650) 724-3681 Stanford, CA 94305-4045 email: redward at stanford.edu From shiwei20012002 at yahoo.com Tue Apr 12 16:33:24 2005 From: shiwei20012002 at yahoo.com (Wei Shi) Date: Tue, 12 Apr 2005 16:33:24 -0700 (PDT) Subject: Au sputter Message-ID: <20050412233324.70478.qmail@web21207.mail.yahoo.com> Hi, I am trying to coat a layer of Au on common glass, but still want to keep it transparant under human's vision. Does any buddy know: 1. What is the maximum thickness I can coat? 2. Do you know any vendor? Thanks, Wei --------------------------------- Do you Yahoo!? Make Yahoo! your home page -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Wed Apr 13 08:05:52 2005 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 13 Apr 2005 08:05:52 -0700 Subject: Au sputter In-Reply-To: <20050412233324.70478.qmail@web21207.mail.yahoo.com> References: <20050412233324.70478.qmail@web21207.mail.yahoo.com> Message-ID: <425D3550.1040004@snf.stanford.edu> Subject: Re: Au sputter From: Dan Grupp Date: Tue, 12 Apr 2005 18:50:20 -0700 To: Wei Shi CC: labmembers at snf.Stanford.EDU about 50A is transparent, perhaps as much as 100A under bright light. Au transmits in the blue-green (it has a broad bell-shaped transmission curve), so it makes great sunglasses (hence space helmet visors)! No IR or UV. It is ez to use Metallica or Innotec for this. -Dan Wei Shi wrote: > Hi, > > I am trying to coat a layer of Au on common glass, but still want to > keep it transparant under human's vision. Does any buddy know: > 1. What is the maximum thickness I can coat? > 2. Do you know any vendor? > > > Thanks, > Wei > > ------------------------------------------------------------------------ > Do you Yahoo!? > Make Yahoo! your home page > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From salazarj at stanford.edu Wed Apr 13 18:49:50 2005 From: salazarj at stanford.edu (Salazar Armando Jones) Date: Wed, 13 Apr 2005 18:49:50 -0700 Subject: missing backpack Message-ID: <1113443390.425dcc3e40bbf@webmail.stanford.edu> To all labmembers: If you mistakingly picked up the wrong backpack from the bench outside of the lab between 3:00-6:00 p.m., contact: Salazar A. Jones (650) 248-0343 salazarj at stanford.edu Thanks. From salazarj at stanford.edu Wed Apr 13 19:20:01 2005 From: salazarj at stanford.edu (Salazar Armando Jones) Date: Wed, 13 Apr 2005 19:20:01 -0700 Subject: backpack returned! Message-ID: <1113445201.425dd3512f877@webmail.stanford.edu> To all labmembers: The backpack has been returned. It was mistakingly picked up, just as I thought. -Salazar A. Jones salazarj at stanford.edu From lll2002 at stanford.edu Thu Apr 14 11:00:23 2005 From: lll2002 at stanford.edu (liangliang li) Date: Thu, 14 Apr 2005 11:00:23 -0700 Subject: about the impedance analyzer or RLC meter Message-ID: <6.1.2.0.2.20050414105641.01b59e70@lll2002.pobox.stanford.edu> Dear friends: I am looking for an impedance analyzer or RLC meter on campus. I want to measure the resistance or inductance of my device at 100 MHz. Anyone knows if there is a machine at Stanford? Thank you! best regards liangliang li From daniel.francis at group4labs.com Thu Apr 14 12:15:28 2005 From: daniel.francis at group4labs.com (daniel.francis at group4labs.com) Date: Thu, 14 Apr 2005 14:15:28 -0500 Subject: missing camera Message-ID: <20050414191529.10EC77C7C@sm4app04.siteprotect.com> Dear labmembers I forgot my camera (digital Fuji S-3000, with my phone number 510 579 6859 on the lens cover and body) in the lab last night across from wbgaas and this morning it was missing. If anyone moved it or otherwise could you please return it to me or Maureen. I have all the pictures from my son's birthday party, and would hate to do w/o them. Also, it has been a bad week for me, someone just took my motorcycle for a joy ride, and left it nearly unrecognizable. So, make my week, drop it off in the lab or with Maureen or call me or put it back or if you see it somewhere in the lab give me a call or send me an email or.... Sorry for the mass mailing, and I appreciate any help. Daniel Francis daniel at francis.com 510 579 6859 From pcatryss at stanford.edu Tue Apr 19 17:59:41 2005 From: pcatryss at stanford.edu (Peter Catrysse) Date: Tue, 19 Apr 2005 17:59:41 -0700 Subject: Bump bonding/unpackaged photodiode array Message-ID: <200504200059.j3K0xhUd000708@smtp1.Stanford.EDU> > Subject: bump bonding/unpackaged photodiode array > > We are building a readout prototype for photodiode arrays in standard CMOS > 0.18u process and looking for companies who can offer > > 1) bump bonding of photodiode array with a pitch better than 10um (at chip > level) > 2) unpackaged photodiode arrays > > The chip consist of an array of 32x6 readout pixels; each pixel is > 30ux140u > and the total chip area is 2mmx2mm. > > We appreciate if someone can point us to any company/facility that can > help > us in that regard. Please contact Sam Kavusi . > > Thanks, > Sam Kavusi > Research Assistant > Room 257, Packard Electrical Engineering Building, > 350 Serra Mall, > Stanford, CA 94305 > Phone: (650) 725-9696 > Fax: (650) 724-3648 > Research page: > http://isl.stanford.edu/groups/elgamal/group_research/sam/home_sam.html From vlordi at gmail.com Wed Apr 20 14:43:13 2005 From: vlordi at gmail.com (Vincenzo Lordi) Date: Wed, 20 Apr 2005 14:43:13 -0700 Subject: scrap chips Message-ID: Hi, I am performing some ribbon bonding tests and was wondering if anyone has any scrap chips they could donate with close to the following specs. Commercially-fab'd CMOS (e.g., National) chips may be the closest thing, if anyone has some old scraps. Ideally, I would want: 700um thick Si, TiN-coated Al pads 75-150um wide, pads 20-40um from chip edge, 1-3um (polyimide) passivation layer surrounding pads. I don't care what's on the rest of the chip. If you might have something close, please email me, and I'll try to determine if it could be useful for me. Thanks, -Vince From vidyagv at gmail.com Wed Apr 20 14:43:39 2005 From: vidyagv at gmail.com (Vidya V) Date: Wed, 20 Apr 2005 14:43:39 -0700 Subject: Interconnect - solder bumps Message-ID: <616a357905042014437f56621d@mail.gmail.com> Hello everyone, We are trying to make a wafer stack using two Silicon wafers using wafer bonding, and make some interconnects between them. Have any of you done something silimar before? Also, Have any of you worked on making solder bumps before? we would be glad for any kind of suggestions. Thanks! -- Srividya Venkatesh Graduate Assistant,EE UTA "Self-discovery comes when man measures himself against an obstacle" From wong at ee.stanford.edu Thu Apr 21 09:38:03 2005 From: wong at ee.stanford.edu (Simon Wong) Date: Thu, 21 Apr 2005 09:38:03 -0700 Subject: Seminar - Sub-Lithographic Semiconductor Computing Systems Message-ID: <6.2.0.14.2.20050420152252.033c6ac0@eemail.stanford.edu> Special Seminar sponsored by Stanford 3D-IC Program 5pm, April 26, Tuesday; CISX Auditorium TITLE: Sub-Lithographic Semiconductor Computing Systems Prof. Andre' DeHon, Computer Science, Caltech http://www.eas.caltech.edu/fac_d-h.html#d ABSTRACT: How Can We Build Nanometer Scale Computing Devices? Enabled by advances in our basic scientific understanding at the molecular and atomic scales, we can now engineer designed nanostructures without using lithography. Key features can be a few nanometers wide---a few silicon atoms wide, perhaps the ultimate scale for devices. This allow us to design computing components without the costs or limits of ultra-fine lithography. Design at this scale, however, will not simply be an extension of our familiar VLSI design. We may not be able to directly pattern complex features, but rather must exploit basic physical properties to define feature sizes, self-assembly to create ordered devices, and post-fabrication reconfigurability to define functionality and mask defects. This creates new challenges for design and exposes a different cost structure which motivates different computing architectures than we found efficient in conventional, lithographically patterned silicon. I will review the emerging nanoscale fabrication building blocks, sketch a hybrid fabrication scheme which uses these building blocks along with lithography, and present a plausible architecture for nanoscale electronics based on silicon nanowires. I demonstrate that these nanoscale constructs are sufficient to provide universal logic functionality with all logic and signal restoration operating at the nanoscale. From tberg at snf.stanford.edu Thu Apr 21 13:16:10 2005 From: tberg at snf.stanford.edu (Ted Berg) Date: Thu, 21 Apr 2005 13:16:10 -0700 Subject: LOST PDA Message-ID: <42680A0A.5000708@snf.stanford.edu> Hello all, One of the Raith Field service engineers has lost his PDA from the ebeam room. If anyone picked it up for safekeeping please let myself or Maureen Baran know so it can be returned. It was lost Tuesday evening. It has important contact information for Field service. Thanks for your help. ted From jenwang at stanford.edu Thu Apr 21 15:18:57 2005 From: jenwang at stanford.edu (Jen-Shiang Wang) Date: Thu, 21 Apr 2005 15:18:57 -0700 Subject: Thin poly film structure References: Message-ID: <002d01c546c0$1cc1b850$0100000a@IBMB86681457DE> Hi, Does anyone have exerience with making mechanical structures (MEMS) with a poly thin film with a submicon (<500nm) thickness at SNF? If you do have experience, do you have info on grain and stress issues? Any infomation is appreciated. Thanks, Jen-Shiang From ankurjn at stanford.edu Mon Apr 25 10:09:18 2005 From: ankurjn at stanford.edu (Ankur Jain) Date: Mon, 25 Apr 2005 10:09:18 -0700 (PDT) Subject: anyone has spare wafers with thermal oxide? Message-ID: Hello labmembers, I need two or three 4 inch Si wafers with thermal oxide grown on them for an etch rate characterization experiment. If you have any 4 inch Silicon wafer with thermal oxide on it that you are not going to use, I would appreciate it if you could donate it to me. I can buy you equivalent blank Silicon wafers. Oxide thickness of 1.0 microns or more would be ideal, though I could use thinner ones too. Its fine if the wafer is gold contaminated. Please email me back if you can help. thanks, Ankur. ************************************************************************* ANKUR JAIN Graduate Student Microscale Heat Transfer Laboratories Residence: Room 201, Building 530 126 Blackwelder Ct, Apt 902 Stanford, CA-94305 Stanford, CA - 94305 Ph: 650-736-0044 Cell Ph: 650-799-8986 http://www.stanford.edu/~ankurjn From dwlee at stanford.edu Tue Apr 26 08:06:39 2005 From: dwlee at stanford.edu (Dok Won Lee) Date: Tue, 26 Apr 2005 08:06:39 -0700 Subject: Does anyone have used 8" wafers to spare? Message-ID: <1114527999.426e58ff15ca1@webmail.stanford.edu> Hello labmembers, I am looking for two 8" wafers for the use in the curvature measurement. Their properties and process history are not critical. If you have used 8" wafers that you do not need any more, please let me know (dwlee at stanford.edu, 723-4015). Thank you. Regards, Dok Won From angela.mcconnell at stanford.edu Tue Apr 26 13:57:00 2005 From: angela.mcconnell at stanford.edu (Angie McConnell) Date: Tue, 26 Apr 2005 13:57:00 -0700 Subject: Ph.D. Oral Examination Message-ID: <6.0.1.1.2.20050426133846.030c3770@adm11.pobox.stanford.edu> Stanford University Ph.D. Oral Examination "Thermal Properties of Micro- and Nanoscale Materials" Angela D. McConnell Mechanical Engineering Department Thermosciences Division Thornton 110 Friday, April 29, 2005 8:00 AM - 9:00 AM (Refreshments at 7:45 AM) In the drive to improve the performance of integrated circuits and microelectromechanical systems (MEMS), device designers have continued to decrease component dimensions to micrometer and nanometer lengthscales. However, as devices become smaller, they tend to experience increased thermal loads due to higher current densities generating heat in smaller volumes. This results in elevated temperatures that are sufficient to significantly influence device performance and also adversely affect long-term reliability and stability. In this way, heat transfer has become a critical design constraint that limits the performance of modern electronic devices. Heat transport models with accurate thermal property data are required to enable designers of integrated circuits and MEMS to effectively manage heat transfer. This thesis details research into the thermal properties of two materials at the micro- and nanoscale: thin polycrystalline silicon films and carbon nanotubes. Thin doped polycrystalline silicon films are common in MEMS and integrated circuit applications. Previous studies show that film processing conditions strongly influence the thermal conductivity by altering the polysilicon microstructure, but existing thermal conductivity data for doped polysilicon films in the literature is difficult to quantitatively compare because relevant microstructural details such as impurity concentrations and grain sizes and shapes are not reported. The current study quantifies the relative effects of impurities and grain boundaries on the thermal conductivity of LPCVD polysilicon films of thickness near 1 micron doped with boron and phosphorus at varying concentrations for a range of temperatures. Thermal conductivity of the polysilicon films is measured using Joule heating and electrical resistance thermometry in a suspended membrane structure. The data shows strongly reduced thermal conductivity values at all temperatures compared to similarly doped single-crystal silicon films, indicating that phonon scattering on grain boundaries is a dominant factor in the polysilicon thermal resistance. Further analysis using a thermal conductivity model based on the Boltzmann transport equation reveals that phonon transmission through the grains is high at low temperatures, leading to large phonon mean free paths and higher than expected thermal conductivity. Carbon nanotubes represent a promising area for nanotechnology research and development due to their high electrical conductivity, tensile strength, and thermal conductivity. However, it is difficult to extract accurate properties of an individual single-walled carbon nanotube (SWNT) from the existing experimental data since most of the measurements are for bulk specimens comprising multiple nanotubes. In the current study, thermal conductance of an individual SWNT is measured using AC electrical resistance thermometry in a MEMS-based device, which comprises a nanotube bridging two heavily doped, free-standing polysilicon legs. Individual nanotubes are grown directly on the device using chemical vapor deposition with iron particles as the growth catalyst. Electrical measurements from the setup are processed using a steady-periodic model of heat generation and heat transfer in the structure to compute temperatures, heat fluxes and thermal properties for the system. The measurement approach is validated using thin silicon nitride filaments of known thermal conductivity. The resulting data for an individual SWNT represents the intrinsic conductance of an isolated nanotube. Comparing this with data for SWNT bundles from the literature indicates that intertube coupling can decrease the intrinsic conductance of the constituent nanotubes in a bundle by more than two orders of magnitude. From zia at stanford.edu Wed Apr 27 15:12:33 2005 From: zia at stanford.edu (Rashid Zia) Date: Wed, 27 Apr 2005 15:12:33 -0700 Subject: Announcement: Rashid Zia, Doctoral Defense In-Reply-To: <6.0.1.1.2.20050223144918.01c67bb0@smillard.pobox.stanford.edu> Message-ID: <200504272212.j3RMCRED022210@smtp-roam.Stanford.EDU> Hello everyone, I will be defending my dissertation this Friday morning. Please attend if you are interested. Thanks, Rashid. Department of Electrical Engineering University Ph.D. Dissertation Defense Speaker : Rashid Zia (Advisor : Prof. Mark L. Brongersma) Title : ?Resolving the Subwavelength Transport of Light: Surface Polariton Optics and Near-Field Microscopy? Date : April 29, 2005 Time : 9:30am (Refreshments at 9:15am) Place : Packard, Room 101 For over three hundred years, the optical microscope has provided scientists with a uniquely intuitive tool for observing microscopic biology, chemistry, and physics. Unfortunately, the resolution of conventional optical imaging is limited by diffraction and uncertainty to roughly half the wavelength of light /2n). This diffraction limit also restricts the ( optical components which have enabled the telecommunications?minimum size of integrated revolution. Not surprisingly, there has been significant effort devoted to circumventing the diffraction limit for both optical characterization and photonic devices. In the past two decades, the scanning near-field optical microscope (SNOM) has been developed to image samples with subwavelength resolution, [1] and more recently, the coupling of light to surface polaritons has been suggested as a method to realize subwavelength optical circuits. [2] Such research not only promises to enable unparalleled control over light-matter interactions at the nanoscale, but also provides a unique regime in which to reexamine the fundamental principles of optical physics. To illustrate the potential of nanophotonics and near-field optics, two related studies on surface polariton optics and near-field microscopy will be reviewed. Surface Polariton Optics: Guiding Light with Metal Surface plasmon-polaritons and surface phonon-polaritons have received much attention for their ability to guide electromagnetic energy at optical and infrared frequencies, respectively. It has been suggested that surface polariton modes are not diffraction limited, and specifically, that surface plasmon modes supported by metal stripe waveguides are inconsistent with a ray-optics interpretation of guided wave phenomena. However, we have recently derived solutions for the plasmon modes which suggest an interpretation consistent with conventional waveguide theory, [3] and we present a dielectric waveguide model for guided polariton optics. [4] Leveraging this physical model, we have designed a variety of plasmonic devices analogous to dielectric integrated optical components. To substantiate a diffraction limit for surface polaritons, we present near-field images of these structures obtained by photon scanning tunneling microscopy (PSTM). Near-Field Microscopy: Probing Optical Fields Despite the continued improvement of near-field optical instrumentation, the interpretation of SNOM/PSTM images remains a complex process. One must deconvolve the effects of probe-sample interactions from an image to develop a precise, quantitative analysis of acquired data. Moreover, as object dimensions become significantly smaller than the wavelength of light, the conventional interpretation of near-field images as measurements of the localized light intensity breaks down. For light confined by sub-wavelength structures, we have shown that PSTM measurements are complicated by the preferential sensitivity of near-field probes to particular field components and spatial frequencies. [5] However, through a novel formulation of the probe?s response function, we demonstrate that preferential scattering from the near-field can be predicted and, thus, that individual components of electromagnetic waves can be imaged with subwavelength resolution in the near-field. [6] References [1] E. Betzig and J. K. Trauhnan, Science 257 (1992), 189. [2] W. L. Barnes, A. Dereux, and T. W. Ebbesen, Nature 424 (2003), 824. [3] R. Zia, M.D. Selker, and M.L. Brongersma. Phys. Rev. B 71 (2005), 165431. [4] R. Zia, A. Chandran, and M.L. Brongersma. To be appear in Opt. Lett. 30 (2005). [5] R. Zia, J. A. Matteo, L. Hesselink, and M. L. Brongersma, Near-Field Optics Conf. (Seoul: 2004). [6] R. Zia, J. A. Matteo, L. Hesselink, and M.L. Brongersma. In preparation. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: RZia_Defense_Abstract.pdf Type: application/pdf Size: 23763 bytes Desc: not available URL: