Seminar - Sub-Lithographic Semiconductor Computing Systems

Simon Wong wong at ee.stanford.edu
Thu Apr 21 09:38:03 PDT 2005


Special Seminar sponsored by Stanford 3D-IC Program

           5pm, April 26, Tuesday;  CISX Auditorium


TITLE:  Sub-Lithographic Semiconductor Computing Systems

      Prof. Andre' DeHon, Computer Science, Caltech
        http://www.eas.caltech.edu/fac_d-h.html#d


ABSTRACT:

How Can We Build Nanometer Scale Computing Devices?

Enabled by advances in our basic scientific understanding at the molecular
and atomic scales, we can now engineer designed nanostructures without
using lithography.  Key features can be a few nanometers wide---a few
silicon atoms wide, perhaps the ultimate scale for devices.  This allow us
to design computing components without the costs or limits of ultra-fine
lithography.  Design at this scale, however, will not simply be an
extension of our familiar VLSI design.  We may not be able to directly
pattern complex features, but rather must exploit basic physical properties
to define feature sizes, self-assembly to create ordered devices, and
post-fabrication reconfigurability to define functionality and mask
defects.  This creates new challenges for design and exposes a different
cost structure which motivates different computing architectures than we
found efficient in conventional, lithographically patterned silicon.  I
will review the emerging nanoscale fabrication building blocks, sketch a
hybrid fabrication scheme which uses these building blocks along with
lithography, and present a plausible architecture for nanoscale electronics
based on silicon nanowires.  I demonstrate that these nanoscale constructs
are sufficient to provide universal logic functionality with all logic and
signal restoration operating at the nanoscale.





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