From ben.jian at arrayedfiberoptics.com Tue Feb 1 01:49:42 2005 From: ben.jian at arrayedfiberoptics.com (ben.jian) Date: Tue, 01 Feb 2005 01:49:42 Subject: very deep etching of fused silica Message-ID: <20050201014942.12084.qmail@server266.com> Hi, We are trying to etch microlenses on fused silica wafer. The height of the microlens is very large - 100 micron tall. The diameter of the microlens is also large - 3.8mm. We think this is definitely not doable at SNF. Does anyone know where we can go to etch such a tall microlens in fused silica? Thanks. Ben From jrosolov at alum.mit.edu Tue Feb 1 12:46:29 2005 From: jrosolov at alum.mit.edu (Julia R. Greer) Date: Tue, 1 Feb 2005 12:46:29 -0800 Subject: Does anyone know about an Ar+ plasma tool? Message-ID: <1107290789.41ffeaa534ad0@webmail-imap.stanford.edu> Hello fellow labmembers, I was wondering if anyone knows of any low-energy Ar+ plasma tool on campus. I just need to sputter some surface damage off of my gold samples, so if there is such a tool available somewhere, I would really appreciate it! Thank you! Julia R. Greer Ph.D. Candidate in Materials Science and Engineering Stanford University (415) 26-JULES From choonghoyu at mail.utexas.edu Wed Feb 2 00:01:36 2005 From: choonghoyu at mail.utexas.edu (Choongho Yu) Date: Wed, 2 Feb 2005 00:01:36 -0800 Subject: SrTiO3 Etch References: <20050114041850.62516.qmail@web21202.mail.yahoo.com> <41E7E973.806@snf.stanford.edu> Message-ID: <002701c508fd$6bc248d0$6500a8c0@VALUEDB8CC434B> Hello SNF labmembers, Does anyone know receipes for SrTiO3 etch? I prefer dry etch. Thank you in advance. CY From ankurjn at stanford.edu Tue Feb 8 12:24:25 2005 From: ankurjn at stanford.edu (Ankur Jain) Date: Tue, 8 Feb 2005 12:24:25 -0800 (PST) Subject: vendors for NiTi sputter deposition? Message-ID: Hello labmembers, I am looking for a vendor (preferably local) that can sputter a few microns of NiTi (Nickel-Titanium Alloy) on Silicon wafers. If you know someone who can do this, I would appreciate knowing about it. thanks, Ankur. ************************************************************************* ANKUR JAIN Graduate Student Microscale Heat Transfer Laboratories Residence: Room 201, Building 530 126 Blackwelder Ct, Apt 902 Stanford, CA-94305 Stanford, CA - 94305 Ph: 650-736-0044 http://www.stanford.edu/~ankurjn From shott at snf.stanford.edu Wed Feb 9 08:57:43 2005 From: shott at snf.stanford.edu (John Shott) Date: Wed, 09 Feb 2005 08:57:43 -0800 Subject: New Secure version of xReporter .... Message-ID: <420A4107.9040706@snf.stanford.edu> An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Thu Feb 10 09:10:52 2005 From: mbaran at stanford.edu (Maureen Baran) Date: Thu, 10 Feb 2005 09:10:52 -0800 Subject: Cell Phone Found in Lab Message-ID: <200502101710.j1AHApxr030783@smtp3.Stanford.EDU> This morning a cell phone was found in the lab. If you are missing your phone and you think it's yours, please come and claim it. I am in cubicle #41. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Thu Feb 10 09:17:33 2005 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 10 Feb 2005 09:17:33 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 2/15/05 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "ESD protection in advanced CMOS technology" JUNG-HOON Chun Stanford University Tuesday, February 15, 2005 4:15 p.m. Building 380, Room 380Y ABSTRACT Ongoing scaling of CMOS technology has imposed more stringent requirements on ESD protection devices. At the same time, performance of the circuits can be seriously compromised by the protection devices. In this talk, after giving a short introduction to ESD phenomenon and general protection strategies I will summarize recent accomplishments of ESD related research in CIS, which cover various 1)device engineering and 2)circuit design issues. 1) Electrothermal TCAD simulation and compact modeling of advanced protection devices will be discussed. ESD simulation examples with a new physical model (temperature dependent contact resistance model) and strained Si/relaxed Si1-xGex MOSFET will be presented. I will also describe and analyze ESD failure phenomena emerging in 130nm and 90nm technology, such as PMOS ESD failure, coupling of ESD devices through substrates etc. 2) Circuit design issues related to ESD with emphasis on high-performance interface circuits for RF and A-to-D applications. Recent accomplishments of this research include: considerations of LNA(narrow and broadband) design and matching networks, and dynamic range and linearity considerations of ADCs. From adhikari at stanford.edu Thu Feb 10 12:11:05 2005 From: adhikari at stanford.edu (Hemant Adhikari) Date: Thu, 10 Feb 2005 12:11:05 -0800 Subject: Ge(111) Message-ID: <6.1.2.0.2.20050210120843.02012740@adhikari.pobox.stanford.edu> Hi, Does anyone of you have some pieces of Ge(111) lying around that you can spare. (I don't need the whole wafer). Or could you tell me where can I buy Ge(111) from? thanks, hemant From daesung at stanford.edu Thu Feb 10 12:34:40 2005 From: daesung at stanford.edu (Daesung Lee) Date: Thu, 10 Feb 2005 12:34:40 -0800 Subject: Ph. D oral exam: Daesung Lee (Monday, Feb. 14, 2 pm) Message-ID: <006d01c50faf$f304f910$185540ab@Daesung> University Ph.D. Oral Examination DESIGN AND FABRICATION OF SOI-BASED MICROMIRRORS FOR OPTICAL APPLICATIONS Daesung Lee, Department of Electrical Engineering Stanford University Monday, February 14, 2005, 2:00pm - 3:00pm Packard 101 (Refreshments served at 1:45pm) Abstract In this talk, we present the fabrication processes and designs of two types of Silicon-on-insulator (SOI)-based micromirrors for optical applications: Single-axis, two-axis scanning mirrors actuated by self-aligned vertical combdrives in double SOI layers and MEMS actuated vertical mirrors for optical bench technology MEMS scanning mirrors enable a variety of optical applications including displays, confocal microscopy, and optical fiber switches. In many of these applications, mirrors require optically flat surface, large actuating force, and large deflection angle. High aspect ratio vertical combdrive actuators in SOI layers offer these desired features. Electrostatic actuators exhibit an important behavior called pull-in which limits the maximum stable deflection. Analytical derivation shows that the alignment of two comb sets in the vertical combdrive is critical because the misalignment reduces the maximum stable deflection. In the first part of the talk, we present the fabrication process and design of vertical combdrives with self-aligned comb sets in double SOI layers. The two oxide layers between the device layers provide electrode isolation and etch stops for thickness control. With three masks from the front-side of the wafers, we demonstrated mirrors capable of a single-axis, bi-directional rotation and piston. Furthermore by adding a non-critical backside etch, we demonstrated two-axis, bi-directional gimbaled scanning mirrors. Double-stacked SOI layers are used to provide both electrical isolation and mechanical connections for gimbaled structures. In the second part of the talk, we present the fabrication process of MEMS actuated vertical mirrors with optically very flat surface for optical bench technology. The optical bench technology enables passive alignments of optical components including vertical mirrors, fiber U-grooves, and lens holders, thus reducing the packaging cost significantly. Previously demonstrated applications of this technology include optical switches, variable optical attenuators, and optical phase shifters. DRIE etch in SOI layer is, due to its simplicity, the most widely used technique to fabricate this type of mirror. However, obtaining good optical-quality surfaces with DRIE remains a challenging task. Wet anisotropic etch with KOH of (110) silicon on the other hand, provides close to atomically smooth vertical surfaces, but anisotropic etching only supports fabrication of very simple structures defined by the crystalline orientation of silicon. In this talk, we present the fabrication process of vertical mirrors that uses a combination of KOH and DRIE etches to take advantage of the merits of each process: Vertical mirror surfaces are fabricated by KOH, while the rest of the structures are fabricated by DRIE. The vertical mirrors are fabricated in a (110) silicon device layer of SOI wafers. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: oral_abstract_daesung_lee_Feb14.pdf Type: application/pdf Size: 71398 bytes Desc: not available URL: From harshal at analatom.com Thu Feb 10 11:59:08 2005 From: harshal at analatom.com (Harshal Surangalikar) Date: Thu, 10 Feb 2005 11:59:08 -0800 Subject: question about headway manual resist coater. Message-ID: hello labmembers, I wanted to coat a wafer with a thick resist, 50 um, and then develop it with a soft bake to get features with about 1:1 aspect ratio. I wanted to know if anyone has used a ready recipe for such a coat, or if anyone has done such a process. thanks for your help. harshal. From rcrane at snf.stanford.edu Fri Feb 11 14:55:40 2005 From: rcrane at snf.stanford.edu (Dick Crane) Date: Fri, 11 Feb 2005 14:55:40 -0800 Subject: Recent fire alarms Message-ID: <420D37EC.2080201@snf.stanford.edu> Lab users and building dwellers, We have had two false, fire alarms in the last two days. On Thursday, personnel from the Stanford Fire Marshal's office were performing a routine test of the smoke detectors. An under-the-floor smoke detector retripped 15 minutes after the test was complete, hence the brief, false fire alarm. Today, an individual accidentally tripped a toxic gas shutdown alarm which automatically trips the fire alarm and hence caused the building evacuation and the fire trucks to arrive. Sorry for the inconvenience caused by the false trips. The alarm systems are necessary to ensure the safe operation of the labs of CIS/CISX. Dick From sjo at stanford.edu Tue Feb 15 23:43:18 2005 From: sjo at stanford.edu (Sebastian J. Osterfeld) Date: Tue, 15 Feb 2005 23:43:18 -0800 Subject: Lost my Mask on Feb 6th - anyone seen it? Message-ID: <4212F996.4010007@stanford.edu> I must have forgotten to return my mask to my bin on February 6th, because today I couldn't find it. It's a standard 5" square mask from Paul for the EVAligner, and the name on its case says "S. Osterfeld". Has anyone seen it? In all likelihood it never left the litho area. Thanks for your understanding, Sebastian Osterfeld -- Sebastian J. Osterfeld PhD. Student / Shan X. Wang Group Dept. of Materials Science & Engineering Residential Mailing Address: 334 Olmsted Rd Apt 114 Stanford, CA 94305 Office Mailing Address: McCullough Building, Room 208A 476 Lomita Mall Stanford, CA 94305-4045 Home: (650) 331-1171 (Voice Mail) Cell: (650) 906-1946 Work: (650) 723-2939 Email: sjo at stanford.edu From mse.whu at stanford.edu Wed Feb 16 21:05:04 2005 From: mse.whu at stanford.edu (Wei Hu) Date: Wed, 16 Feb 2005 21:05:04 -0800 Subject: Particle counter needed Message-ID: <1108616704.4214260025deb@webmail.stanford.edu> Dear all, Does anybody know where I can borrow a particle counter to measure the clean grade? Thanks! Wei From guerra at par.stanford.edu Thu Feb 17 10:07:33 2005 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 17 Feb 2005 10:07:33 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 2/22/05 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "Phase-Locked Loop and CDR Design for SOC Applications" JOSEPH INGINO Tuesday, February 22, 2005 4:15 p.m. Building 380, Room 380Y ABSTRACT The trend toward digital systems-on-a-chip (SOCs) with greater levels of integration, higher data rates, and lower supply voltages, has resulted in an increasingly noisy environment in which sensitive circuit blocks, such as phase-locked loops (PLLs), must operate. Noise levels have been further exacerbated by the failure of I/O voltage levels to scale at a rate equal to that of internal core voltages. Moreover, the need to integrate multi-gigabit SERDES interfaces such as XAUI, PCI-express, etc., with digital and mixed-signal SOCs, has resulted in more stringent timing margins, primarily in the forms of jitter limits and lock-time requirements. These factors have resulted in an increasing demand for high-accuracy PLLs, CDRs (clock and data recovery) and other clock-generating/recovery blocks. The first part of this talk describes the various tradeoffs and issues related to the design of PLLs for clock synthesis and clock and data recovery. The second part of the talk presents a method for minimizing a PLL's or CDR's sensitivity to supply noise. On large SOCs, power-supply noise is often the most common and dominant source of jitter or phase-noise on a PLL's output clock. Jitter can be minimized with careful design of the noise sensitive blocks, such as the VCO, in conjunction with regulating the supply to these critical blocks. A PLL that achieves a power-supply-rejection ratio (PSRR) greater than 40 dB while operating up to 6 GHz will be described. The PLL is intended for use in a high-speed SOC that operates at internal clock frequencies exceeding 2 GHz. The high level of noise rejection is achieved with a high-bandwidth voltage regulator that provides a nominally noise-free supply to the PLL's sensitive analog blocks. From shott at snf.stanford.edu Fri Feb 18 16:14:55 2005 From: shott at snf.stanford.edu (John Shott) Date: Fri, 18 Feb 2005 16:14:55 -0800 Subject: Coral servers will be down for 30 minutes on Saturday morning ... Message-ID: <421684FF.8040408@snf.stanford.edu> An HTML attachment was scrubbed... URL: From zxie at snowmass.Stanford.EDU Fri Feb 18 21:32:44 2005 From: zxie at snowmass.Stanford.EDU (Zhigang Xie) Date: Fri, 18 Feb 2005 21:32:44 -0800 (PST) Subject: PhD dissertation defense/Zhigang Xie (Feb 23, wed, 3:30pm) Message-ID: I apologize if you receive multiple copies. DEPARTMENT OF APPLIED PHYSICS UNIVERSITY PhD DISSERTATION DEFENSE Zhigang Xie Research Advisor: Professor James S. Harris Title Integration of Quantum Dots with Microdisk Cavities February 23, 2005 @ 3:30pm in CISX auditorium (CISX 101) ABSTRACT Self-assembled quantum dots growth is a strain-driven phenomenon that can take place in lattice-mismatch epitixial growth. Electrons and holes confined in these nano-scale structures exhibit discrete optical emission that in many ways is similar to atoms, yet with the richness of many-body interactions. In the spontaneous emission regime, this emission can be used in quantum information processing if the optical extracting efficiency is high enough to allow for error correction algorithms and privacy amplification. In contrast, lasing from QDs can be seen at very low threshold powers, possibly providing a unique low power source. Both spontaneous emission and lasing from QDs can be made possible by embedding the QDs into a micro-scale optical cavity. In this talk, I will discuss spontaneous emission and lasing of QDs in a microdisk cavity. When the QD dipole is properly coupled to the cavity mode, the spontaneous emission can be enhanced. For lasing the cavity provides an enhanced photon density. However, in a microdisk cavity the cavity mode is isolated at the disk parameter and for efficient coupling the QDs should be located in this region. To achieve this, we have developed a regrowth technique to place QDs close to the anti-node of microdisk whispering-gallery modes. We observe a decreasing QD perimeter density with decreasing disk diameter: on big disk of 30um, the linear density will saturated to 6/um; while on small disk of 3~4um, there usually will only 1~3 QDs present. Our micro-PL shows well-defined single QD emission signature, as well as a large splitting for neutral excitons emitting with opposite linear polarization. This regrowth technique can provide sharp exciton peaks as well as a cavity Q of 2,000 for the small disk of 3~4 um. I will compare this technique with the normal microdisk fabrication made without regrowth. Using this technique, I will discuss QD lasing in the smallest microdisk (1.8um) reported, with a cavity Q of 10,000. From the cavity mode lines tuning through QD exciton lines, it approves near single QD lasing, usually a Pucell factor of 80 is required to achieve this goal. When the QD is at resonance with a cavity mode, a lasing threshold as low as 10W/cm2, or 300nW for each disk is estimated. From shott at snf.stanford.edu Sat Feb 19 10:32:35 2005 From: shott at snf.stanford.edu (John Shott) Date: Sat, 19 Feb 2005 10:32:35 -0800 Subject: Updated Coral EquipmentStatus panel ... Message-ID: <42178643.6090006@snf.stanford.edu> An HTML attachment was scrubbed... URL: From rissman at stanford.edu Tue Feb 22 12:55:08 2005 From: rissman at stanford.edu (Paul Rissman) Date: Tue, 22 Feb 2005 12:55:08 -0800 Subject: e-beam lithography presentation Message-ID: <5.1.1.5.2.20050222125419.01848e50@rissman.pobox.stanford.edu> There will be a presentation on electron beam lithography by Dr. Tim Groves of Leica on: Friday, March 4th 1 PM CIS 101 The abstract is listed below. Please forward this message on to anyone who you think would be interested in the talk. Paul Rissman >Recent Progress in Electron Beam Lithography of Nanometer Scale Structures > >Dr. Tim Groves, Director of Technology at Leica Microsystems Lithography, >and Consulting Professor of Electrical Engineering at Stanford > >E-beam lithography remains the method of choice for fabricating structures >in the range of 4 nm to 200 nm in size. In additon to having inherently >high resolution, it has the ability to store and print complex patterns, >thus avoiding the cost and cycle time of photomasks. Recent years have seen >an enormous proliferation of commercial and research applications for EBL. >Dr. Groves will describe some of these, along with the capabilities and >limitations of the technology. An open discussion of the EBL needs of the >Stanford community will follow. From guerra at par.stanford.edu Thu Feb 24 16:14:35 2005 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 24 Feb 2005 16:14:35 -0800 (PST) Subject: EE310 Integrated Circuits Seminar, 3/1/05 Message-ID: EE310 Integrated Circuits Technology and Design Seminar "RADAR Before the Magnetron: A Technical History of Allied Radar on the Eve of World War II" Rick Ferranti SRI International Tuesday, March 1, 2005 4:15 p.m. Building 380, Room 380Y ABSTRACT The late 1930's was a period of intense development in high-frequency radio technology, focused by the desperate need for air defense in the impending world conflict. The result of these research efforts was radar - deployed internationally in 1939 - but its full potential was not realized until the invention of the microwave cavity magnetron in 1940. Until then, early WWII radars operated at meter wavelengths, borrowing antenna and circuit technologies from the shortwave and early television disciplines. Using vintage film clips and modern computer analysis, this 45-minute presentation will highlight the technical innovations, operation, and legacies of two of the more famous early radars deployed by the Allies, the British Chain Home and the American SCR-270. BIOGRAPHY Mr. Ferranti is a senior research engineer at SRI International (formerly the Stanford Research Institute) specializing in high frequency through microwave communications and radar systems. He graduated from Santa Clara University, Harvard University and the Massachusetts Institute of Technology, where he was an associate leader of the Air Traffic Control Systems Group at MIT's Lincoln Laboratory. Rick lives in the SF Bay Area with his wife, two sons, and a garage full of old electronics. From xzhuang at stanford.edu Mon Feb 28 17:03:55 2005 From: xzhuang at stanford.edu (Steve Zhuang) Date: Mon, 28 Feb 2005 17:03:55 -0800 Subject: polyimide adhesive Message-ID: <013701c51dfa$8a9669f0$bb5640ab@pky7> Hi all, I'm just wondering if anyone has experience with using polyimide as adhesive to bond two wafers? I'm trying to find a solution to bond a silicon wafer to a quartz carrier wafer and then etch deep trenches on the exposed side of the silicon wafer. I will separate the quartz and the silicon after dicing the wafer. So the bonding is temporary and yet should have good uniformity. Any input will be highly appreciated! Thanks! Steve Zhuang -------------- next part -------------- An HTML attachment was scrubbed... URL: From xpxie at stanford.edu Mon Feb 28 21:15:50 2005 From: xpxie at stanford.edu (xpxie at stanford.edu) Date: Mon, 28 Feb 2005 21:15:50 -0800 Subject: Fw: Had anyone done any dry etching with Lithium niobate in CIS? Message-ID: <000c01c51e1d$bc0a1770$dc5740ab@xxp> Hello, group, Had anyone done any dry etching on lithium niobate wafers to create structures such as ridge waveguides? I was wondering which dry etching machine in CIS is appropriate for it: Amtetcher, Drytek, MRC or else? From literature, the best etchant could be CCl2F2 and the mask could be Cr, Ni or photoresist. CF4+O2, or CHF3 may also work well as the etchant. I need to etch at least 2.5um deep trenches. The etching rate and etching condition would need to try out after a machine is selected. Any suggestions would be greatly appreciated! Xiuping From lwchang at stanford.edu Mon Feb 28 18:45:54 2005 From: lwchang at stanford.edu (Li-Wen Chang) Date: Tue, 1 Mar 2005 10:45:54 +0800 Subject: programmable vaccum oven (P<100mTorr) Message-ID: <028c01c51e08$ca0edaf0$7fb8fea9@IBM4A340690B1D> Hello labmembers: Does anyone know where I can find a programmable vaccum oven (P<100mTorr) on campus? The programmable BlueM oven in snf purges inert gas and does not work under vaccum condition. The temperature range goes around 160~180C for my process. Thank you in advance! Li-Wen Chang -------------- next part -------------- An HTML attachment was scrubbed... URL: