EE310 Integrated Circuits Seminar, 2/15/05

Ann Guerra guerra at
Thu Feb 10 09:17:33 PST 2005

EE310 Integrated Circuits Technology and Design Seminar

"ESD protection in advanced CMOS technology"

	     JUNG-HOON Chun
	   Stanford University

	Tuesday, February 15, 2005
		4:15 p.m.
	Building 380, Room 380Y

Ongoing scaling of CMOS technology has imposed more stringent
requirements on ESD protection devices. At the same time, performance of
the circuits can be seriously compromised by the protection devices.
In this talk, after giving a short introduction to ESD phenomenon and
general protection strategies I will summarize recent accomplishments of
ESD related research in CIS, which cover various 1)device engineering
and 2)circuit design issues.

1) Electrothermal TCAD simulation and compact modeling of advanced
protection devices will be discussed. ESD simulation examples with a new
physical model (temperature dependent contact resistance model) and
strained Si/relaxed Si1-xGex MOSFET will be presented. I will also
describe and analyze ESD failure phenomena emerging in 130nm and 90nm
technology, such as PMOS ESD failure, coupling of ESD devices through
substrates etc.
2) Circuit design issues related to ESD with emphasis on
high-performance interface circuits for RF and A-to-D applications.
Recent accomplishments of this research include: considerations of
LNA(narrow and broadband) design and matching networks, and dynamic
range and linearity considerations of ADCs.

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