EE310 Integrated Circuits Seminar, 2/22/05

Ann Guerra guerra at
Thu Feb 17 10:07:33 PST 2005

EE310 Integrated Circuits Technology and Design Seminar

"Phase-Locked Loop and CDR Design for SOC Applications"


	Tuesday, February 22, 2005
		4:15 p.m.
	Building 380, Room 380Y


The trend toward digital systems-on-a-chip (SOCs) with greater levels of
integration, higher data rates, and lower supply voltages, has resulted in
an  increasingly noisy environment in which sensitive circuit blocks, such
as  phase-locked loops (PLLs), must operate.  Noise levels have been
further exacerbated by the failure of I/O voltage levels to scale at a
rate equal to that of internal core voltages.  Moreover, the need to
integrate multi-gigabit SERDES interfaces such as XAUI, PCI-express, etc.,
with digital and mixed-signal SOCs, has resulted in more stringent timing
margins,  primarily in the forms of jitter limits and lock-time
requirements.  These factors have resulted in an increasing demand for
high-accuracy PLLs, CDRs (clock and data recovery) and other
clock-generating/recovery blocks.  The first part of this talk describes
the various tradeoffs and issues related to the design of PLLs for clock
synthesis and clock and data recovery.

The second part of the talk presents a method for minimizing a PLL's or
CDR's sensitivity to supply noise.  On large SOCs, power-supply noise is
often the most common and dominant source of jitter or phase-noise on a
PLL's output clock.  Jitter can be minimized with careful design of the
noise sensitive blocks, such as the VCO, in conjunction with regulating
the supply to these critical blocks.  A PLL that achieves a
power-supply-rejection ratio (PSRR) greater than 40 dB while operating
up to 6 GHz will be described.  The PLL is intended for use in a
high-speed SOC that operates at internal clock frequencies exceeding
2 GHz.  The high level of noise rejection is achieved with a
high-bandwidth voltage regulator that provides a nominally noise-free
supply to the PLL's sensitive analog blocks.

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