PEUG/TFGU 2005 Annual Symposium

Jim McVittie mcvittie at
Mon Sep 19 10:23:49 PDT 2005

The local AVS plasma etch and thin film users groups are having a one
day symposium on Oct 4th in San Jose. It is a good meeting to attend if
you want to get an overview of state-of-the-art patterning tranfer and
thin film technologies applied to advanced electronic devices. On Oct.
5th there will be a follow on symposium on CMP.  The early registration
fee ($175) ends on Friday Sept. 23. After the 23th the fee goes to $250.
Registration and symposium details are available at The symposium program is below.  Thanks,  Jim

PEUG/TFGU  2005 Annual Symposium--Tuesday, October 4, 2005

DoubleTree Hotel, San Jose, CA


7:30      Registration

8:00      Introduction by PEUG and TFUG Chairs ; Jim
McVittie and Huey-Chiang Liou

 Session I:  Front End--Printing Patterning--Plasma Etch

Session Co-Chair:  Jim McVittie,  Stanford

8:10      Keynote:  "Process Challenges for Advanced FETs", Prof
Tsu-Jae King, UC Berkeley

8:50      "Ge and III-V Device Research for CMOS", Wilman Tsai, Intel

9:20      "Advanced Photoresist Issues", Mark Slezak, JSR Micro

9:50      Break

 Session Co-Chair: Brett Cruden,         NASA

10:10    "Pattern Transfer Integration", Arpan Mahorowala,       IBM

10:40    "The Use of Pattern Transfer Layers for Advanced Processing",
Calvin Gabriel, S. Bell, A. Agarwal, H. Tokuno and L. You,       AMD

11:10    "Why We Need High Frequency Capacitive Coupling Plasma for
Process", Dan Hoffman, S. Shannon, K. Bera,        AMAT

11:40    “In Situ Real-Time Monitoring of Evaporation Induced
Self-Asssembly of Mesoporous Low-Dielectric-Constant SiO2 and Its
Profile Evolution During Plasma Etching’, Prof. Sang Han, University of
New Mexico

12:10    Lunch

Session II:  Low-k --- ;Nanotechnology --- Reliability

Session Co-Chair:  Huey-Chiang Liou,       Intel

1:10      " Plasma Etch Polymer: When Good Polymer Goes Bad”
Jeff Shields, O. del Carpio, J. Foster,    AMD/Spansion
C. Gabriel,     AMD

1:40      "Molecular Caulk: EnablingAspects for Ultra-Low k Dielectric
Integration at 45nm", Jay Senkevich, B.P Carrow, B.W. Woods.   Brewer
D-L Bae, T.S. Cale,     Rensselaer

2:10      "Aurora Low-k Integration with Advanced ALD Barrier", Devendra

Kumar,         ASM

2:40      Break

 Session Co-Chair: Mira Ben-Tsur,   Cypress

3:00      Keynote:  "Nanotechnology for Microelectronics", Meyya
Meyyappan,         NASA

3:40      "Nano-imprinting Technology", Wei Wu,        HP

4:10      “Advanced Back End Integration Issues”, Roey Shaviv, A.
Bayman, T. Mountsier, W. Wu, K. Chattopadhyay, B. van Schravendijk, G.
Alers, G. Dixit and R. Havemann,         Nevellus Systems

4:40      "Computational Modeling of Process Induced Damage During Back
End of Line Wafer Processing", Shahid Rauf,         Freescale

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