From mtang at stanford.edu Fri Dec 1 13:04:58 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 01 Dec 2006 13:04:58 -0800 Subject: Annual End-of-year Party - Friday, 12/8/06 Message-ID: <457098FA.50209@stanford.edu> Greetings everyone! It's almost the end of the year -- and to see it out with cheer, please come to the CIS building party, to be held next Friday, Dec. 8, beginning at 2 pm. There will be snacks and drinks (courtesy of the CIS Affiliates program), games (courtesy of SNF, and including the famous "wafer toss" and "decorate your own holiday wafer ornament"), and a chance to get away from it all for an afternoon. Some people have expressed an interest in bringing international treats and snacks to share -- please feel free to do so! So please reserve the date -- and hope to see you there! Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From sjo at stanford.edu Sun Dec 3 19:54:15 2006 From: sjo at stanford.edu (Sebastian J. Osterfeld) Date: Sun, 03 Dec 2006 19:54:15 -0800 Subject: Good freeware alternative to L-Edit Message-ID: <45739BE7.10109@stanford.edu> Dear SNF Labmembers, If you're designing your own masks, then I'm sure you all have wanted to work from the comfort of your home at times. I have looked at many possible software packages for this, and one stands out that is NOT yet mentioned on the SNF website. So I wanted to point out that this is a very good free (as in freeware) alternative for editing and creating GDS mask files: LayoutEditor, which can be found here for Windows and Linux: Main Page: http://layout.sourceforge.net/ Screen shots: http://layout.sourceforge.net/screenshots/index.html Download: http://sourceforge.net/project/showfiles.php?group_id=121668 I have used it on a bunch of my GDS files, and after a day or two I'm getting the hang of it. Features include: - Circular & Bezier tools and geometries - Boolean operators (A-B, B-A, etc.) - 3D visualization, as long as you set up a dummy cell defining the stacking order - Multiple aligning and snapping features (grid, point, edge, etc.) - Scaling, growing linewidths, merging shapes, rounding corners, etc. - Angle, Area, and Ruler measurements - Design rules - Reflection along arbitrary axis, etc. - Simple keyboard shortcuts What I am still missing over L-Edit is the ability to select multiple shapes with a drag box, however. Also, shape selection is a bit finickier than in L-Edit, i.e. you may have to go to a particular corner of a rectangle to select it. Otherwise it seems really good Hope this helps! I might be able to give tips to new users. -- Sebastian J. Osterfeld PhD. Student / Shan X. Wang Group Dept. of Materials Science & Engineering Residential Mailing Address: 334 Olmsted Rd Apt 114 Stanford, CA 94305 Office Mailing Address: McCullough Building, Room 208A 476 Lomita Mall Stanford, CA 94305-4045 Home: (650) 331-1171 (Voice Mail) Cell: (650) 906-1946 Work: (650) 723-2939 Email: sjo at stanford.edu From mtang at stanford.edu Mon Dec 4 12:42:36 2006 From: mtang at stanford.edu (Mary Tang) Date: Mon, 04 Dec 2006 12:42:36 -0800 Subject: Annual CIS/CISX/SNF Building Party -- Postponed to 12/15/06! Message-ID: <4574883C.3010907@stanford.edu> Hi everyone -- Many apologies... due to a scheduling conflict, we are postponing the building/lab-wide annual party. (It turns out that Marilyn had long ago scheduled an art reception for same afternoon -- and although I'm sure all our partygoers appreciate fine art, it just didn't seem quite courteous to our guest artists to be sweeping up chips off the floor just as their event gets underway...) So, we've rescheduled for the following Friday, Dec. 15, at 2 pm. Everyone in CIS/CISX or SNF is welcome. There will be snacks, games, and a chance to chat -- and if you'd like to bring a special holiday treat to share, it would be especially welcome. Hope to see you all there! Your CIS and SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jennyhu at stanford.edu Mon Dec 4 13:01:35 2006 From: jennyhu at stanford.edu (Jenny Ruey-Chen Hu) Date: Mon, 4 Dec 2006 13:01:35 -0800 Subject: Etching of Al2O3 Message-ID: <1165266095.45748caf29f97@webmail.stanford.edu> Hello SNF labmembers, Does anyone have a recipe for etching Al2O3? I have 1000A Al on top of 10nm Al2O3. Do you know the selectivity of the Aluminum Etchant( WBMETAL ) between Al and Al2O3? Thanks for your help! Sincerely, Jenny From hungtao at stanford.edu Mon Dec 4 16:15:07 2006 From: hungtao at stanford.edu (Hung-Tao Chou) Date: Mon, 4 Dec 2006 16:15:07 -0800 Subject: lost cell phone last night Message-ID: <1165277707.4574ba0bd950f@webmail.stanford.edu> Hi All, I left my cell phone next to PQUEST last night. It is a white Motorala cell phone. Please let me know if you have seen it anywhere. Thanks! Hungtao From mahnaz at stanford.edu Tue Dec 5 09:49:20 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Tue, 05 Dec 2006 09:49:20 -0800 Subject: YES Message-ID: <4575B120.2000606@stanford.edu> Hello all, I just have been told that the YES oven will go down for few hours so they can hook it up to the CORAL system. Sorry for the late notice, is hard to arrange this kind of down time in advance. mahnaz From mtang at stanford.edu Tue Dec 5 13:42:25 2006 From: mtang at stanford.edu (Mary Tang) Date: Tue, 05 Dec 2006 13:42:25 -0800 Subject: Reminder: Lab Cleanup, Dec. 11-19. Message-ID: <4575E7C1.4010305@stanford.edu> Hi everyone -- Just wanted to remind you all (second notice!) of the traditional end-of-year lab cleanup -- and as ever we REALLY need your help! Here are the rules of engagement: 1. All personal items in the cleanroom that are NOT stored inside personal storage bins will be REMOVED from the lab. This includes Work-in-Progress on WIP shelves and labware/glassware stored outside the designated wet bench areas. Staff will begin sweeping the lab next Monday, Dec. 11. If you plan to work in the lab up until shutdown the following week (at 7 am on Monday, Dec. 18), place a RED DOT on any personal items (lab notebooks, wafer boxes, tweezer boxes, etc.) that will you need between Dec. 11 and Dec. 18. RED DOTS are available in the gowning room, near the vacuum sealer. 2. All personal items in the CAD room NOT stored inside personal storage bins will be REMOVED. All personal storage bins must be labeled with your CORAL login and the current date. Any bins which are not labeled with the current date may be removed. Personal storage bins must be plastic (cardboard boxes are not acceptable) and must be placed safely on the storage shelves (any storage boxes on the floor will be removed.) 3. All personal chemicals in the Flammables cabinet and the chemicals passthrough labeled with a date prior to 2006 may be removed. Please take this opportunity to clean out your old chemicals to make way for the new. Again, please do what you can to help out in the cleanup -- so the lab will be a much tidier place in 2007! Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From pruitt at stanford.edu Tue Dec 5 14:02:24 2006 From: pruitt at stanford.edu (Beth Pruitt) Date: Tue, 5 Dec 2006 14:02:24 -0800 Subject: Neural Interface in CMOS Technology - MEMS/mechanics seminar Wed 12/6 at 4:15 Message-ID: Dr. Sadik Hafizovic of ETH Physical Electronics Lab Room 300 Bldg 300 Wed 12/6 at 4:15pm "Neural Interface in CMOS Technology". Abstract: Microelectrode arrays are specially prepared dishes in which neural networks can be grown or brain slices can be placed to record their electrical activity. Additionally, activity in the cultured neurons can be triggered by electrical stimulation. This seminar is about the integration of a microelectrode array for bidirectional communication with electrogenic cells like neurons or cardiomyocytes into a CMOS chip. The cells are cultured directly on top of the chip which features all the electronics to provide a digital data interface. An application of the system that aims at performing information processing with natural neuronal networks is presented. Short Bio: Sadik Hafizovic received his diploma degree in microsystem technology from IMTEK, University of Freiburg, Germany in 2002. He worked on the corresponding diploma thesis in the Tabata Laboratories at the Ritsumeikan University, Japan. In 2002, he joined the Physical Electronics Laboratory at the ETH Zurich in Switzerland, where he received PhD degree in 2006 in electrical engineering for his research on CMOS-based microelectrode arrays for neuron interfaces and atomic-force microscopy. Currently he is working in a post-doctoral position at the Physical Electronics Laboratory on CMOS-based neuron interfaces for information processing with natural neuronal networks. From mtang at stanford.edu Tue Dec 5 14:19:34 2006 From: mtang at stanford.edu (Mary Tang) Date: Tue, 05 Dec 2006 14:19:34 -0800 Subject: High Humidity in Litho Message-ID: <4575F076.10006@stanford.edu> Sorry everyone -- The lithography area is experiencing out-of-spec humidity (52% - nominal spec is 45% with low and high of 40% and 50%, respectively.) According to Facilities, it is because the outside weather is unusually dry and the control system appears to be overcompensating. They are looking into this. In the meantime, please be aware of the humidity problem -- you may want to delay processing of critical layers until humidity returns to normal. Litho Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mahnaz at stanford.edu Tue Dec 5 17:00:14 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Tue, 05 Dec 2006 17:00:14 -0800 Subject: Humidity Message-ID: <4576161E.3010705@stanford.edu> Hello all, The humidity is at 45% in the litho area, this is where I like it to be ( perfect). mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From mihuhou at stanford.edu Tue Dec 5 17:29:36 2006 From: mihuhou at stanford.edu (Ying Chen) Date: Tue, 5 Dec 2006 17:29:36 -0800 Subject: Fw: Please forward the notice of Toshiba-Stanford day to CIS mailing list Message-ID: <053a01c718d5$fd96af00$0100000a@ZHUBAOBAO> ----- Original Message ----- From: "Atsuhiro Kinoshita" To: Sent: Tuesday, December 05, 2006 5:26 PM Subject: Please forward the notice of Toshiba-Stanford day to CIS mailing list > Dear CIS Faculty Members and Students, > > Toshiba-Stanford Day will be held at CIS-X auditorium on > December 15, 2006, in order to introduce Toshiba technologies > to CIS members and to enhance the relationship between > Toshiba and Stanford University. > > We, Toshiba, will present 9 papers. The papers will be discussing > state-of-the-art TOSHIBA technologies as well as physical > mechanisms behind present/future MOSFETs. All the papers > are based on IEDM 2006 presentations. > Several managers at Toshiba Corporation will also attend the > events. > In addition, Stanford professors will present recent research > topics at Stanford University. > > Every CIS faculty members and students are very welcome to join > this event. > > RSVP to Gabrielle Scofield via email at: gabrielles at ee.stanford.edu > > > --------------------------------------------------------------------- > > Toshiba-Stanford Day > CISX Auditorium, December 15, 2006 > > 8:30 am Breakfast > > Session I: Introduction (9:00am-9:30am) > > 9:00 am Introduction > Professor Yoshio Nishi, Stanford University, & Noburu Fukushima, TOSHIBA > 9:15 am Overview of TOSHIBA R&D Activities on Advanced LSI Technologies > Akira Nishiyama, TOSHIBA > > Session II: Advanced MOSFETs (9:30pm-12:30pm) > > 9:30 am Recent Research Topics on High Mobility Channels in Stanford > University > Professor Krishna C. Saraswat, Stanford University > 10:00 am Comprehensive Study on Injection Velocity Enhancement in > Dopant-Segregated Schottky MOSFETs > Atsuhiro Kinoshita, TOSHIBA > 10:30 am Coffee Break > 11:00 am 1 nm NiSi/Si Junction Design based on First-Principles > Calculation for Ultimately Low Contact Resistance > Takashi Yamauchi, TOSHIBA > 11:30 am Guideline for Low Temperature Operation Technique to Extend > CMOS Scaling s > Akira Hokazono, TOSHIBA > 12:00 pm A 45nm High Performance Bulk Logic Platform Technology (CMOS6) > using Ultra High NA(1.07) Immersion Lithography with Hybrid > Dual-Damascene Structure and Porous Low-k BEOL > Hideaki Nii, TOSHIBA > 12:30 pm Lunch > > Session III: Advanced Gate Stack & Others (2:00pm-5:20pm) > > 2:00 pm Recent Research Topics on High-k and Metal Gates in Stanford > University > Paul C. McIntyre, Stanford University > 2:30 pm Impact of Very Low Hf concentration (Hf=6%) Cap Layer on > Performance and Reliability Improvement of HfSiON -CMOSFET with EOT > scalable to 1nm > Motoyuki Satoh, TOSHIBA > 3:00 pm Practical Work Function Tuning Based on Physical and Chemical > Nature of Interfacial Impurity in Ni-FUSI/SiON and HfSiON systems > Yoshinori Tsuchiya, TOSHIBA > 3:30 pm Coffee Break > 4:00 pm Universal Relationship between Low-Field Mobility and High-Field > Carrier Velocity in High-k and SiO2 Gate Dielectric MOSFETs > Masumi Saitoh, TOSHIBA > 4:30 pm Carrier Transport in (110) nMOSFETs: Subband Structures, > Non-Parabolicity, Mobility Characteristics, and Uniaxial Stress Engineering > Ken Uchida, TOSHIBA > 4:50 pm Floating Body RAM Technology and its Scalability to 32nm Node > and Beyond > Tomoaki Shino, TOSHIBA > 5:20 pm Closing Remarks & Adjourn > Professor Nishi, Stanford University, & Noburu Fukushima, TOSHIBA > > --------------------------------------------------------------------- From hoyeolcho at gmail.com Wed Dec 6 12:29:59 2006 From: hoyeolcho at gmail.com (Hoyeol Cho) Date: Wed, 6 Dec 2006 12:29:59 -0800 Subject: Reminder: Ph.D. Oral Defense Announcement--Tomorrow Dec. 7 10:00 Packard 101--Hoyeol Cho Message-ID: *Performance Comparison between Copper, Carbon Nanotube, and Optics for Off-chip and On-chip Interconnects* Ph.D. Candidate: Hoyeol Cho Advisor: Krishna C. Saraswat Date: Thursday, Dec. 7, 2006 10:00 am Location: Packard 101 (Refreshment will be served at 9:45 am ) *Abstract *? For more than 30 years, the performance of silicon integrated circuits has improved at an astonishing rate. The number of functions per chip has grown exponentially, dramatically bringing down the cost per function. However, for the first time the relentless scaling paradigm is threatened by fundamental limits including excessive power dissipation, insufficient communication bandwidth and signal latency. Many of these obstacles stem from the physical limitation of Cu-based electrical wires, making it imperative to examine alternate interconnect schemes for future ICs. The two most important novel potential candidates are optical and carbon nanotube (CNT)-based interconnects. Optical interconnect due to its high bandwidth, low signal attenuation and cross talk, is an ideal candidate to tackle the challenges imposed by electrical wiring for both off-chip and possibly on-chip application. Because the modern ICs require an ever-increasing system bandwidth and have a large power density, a realistic study of performance comparison between electrical and optical interconnects is of paramount importance. In addition, such a comparison framework aids in setting clear goals on the requirements of opto-electronic devices to deliver a superior performance than their electrical counterparts. For on-chip application, o ptical interconnects can potentially reduce latency, provide high-bandwidth at relatively low power. However, an optical waveguide, has a relatively larger size (pitch~0.6 m m), making it difficult to provide high bandwidth density. This can be mitigated using wavelength division multiplexing (WDM). CNT interconnects, on the other hand, have the flexibility of being implemented in the same size scale as the existing Cu on-chip wires, hence possibly can provide high bandwidth density. In addition they have the advantage of having a large electron mean free path, hence low resistance. This can result in low latency compared to Cu/low-K counterpart. In this talk, for on-chip application, we compare CNT and optical interconnects with Cu interconnects using both commonly used metrics: latency and power and a compound metric which captures system requirements more efficiently. The necessity of compound metrics is motivated by the fact that larger bandwidth and a smaller latency can be obtained using more area resources. Hence area normalization is necessary. In addition, the total power budget can also be used to increase the aggregate bandwidth, making power normalization also imperative. Hence, we use bandwidth density/latency/power as our compound metric. In the future, because of multi-core architecture, the designers care about the bandwidth density, latency and power dissipation of global communication. We extensively examine the impact of device parameters-modulator and detector capacitances for optics, materials parameters-mean free path and packing density for CNTs, and system parameters-global clock frequency and switching activity on both commonly used and the compound metrics. We find that at 22nm technology node small detector and modulator capacitances for optical interconnects (~10fF) yields superior, at least comparable, performance with CNTs (practical, electron mean free path of 0.9m m) and Cu for greater than 35% and 20% switching activity, respectively. However, improving mean free path of CNTs (~2.8 mm) increases this crossover switching activity to 80%. Finally, for off-chip application, we compare high speed optical and electrical interconnect using power vs. bandwidth. We find that beyond critical length, power optimized optical interconnects dissipates lower power compared to high-speed electrical signaling scheme. Beyond 32nm technology node with its commensurate bandwidth, optical interconnect becomes favorable for the distance less than 10cm correspondent to inter-chip communication. This analysis of the impacts of device/system parameters on critical length gives system/device designer the evaluation framework of the performance of the system. -------------- next part -------------- An HTML attachment was scrubbed... URL: From altug at stanford.edu Wed Dec 6 14:13:02 2006 From: altug at stanford.edu (Hatice Altug) Date: Wed, 6 Dec 2006 14:13:02 -0800 Subject: Do you have Ammonium Sulfide or/and thioacetamide ? Message-ID: Hello, Does any one have ammonium sulfide and/or thioacetamide (formula: (NH4)2Sx and CH3CSNH2 ) that they can share a small amount? It can be either in crystal form or already dissolved. Thank you, Hatice From nmehenti at stanford.edu Thu Dec 7 00:47:47 2006 From: nmehenti at stanford.edu (Neville Mehenti) Date: Thu, 07 Dec 2006 00:47:47 -0800 Subject: Ph.D. Oral Examination -- Neville Z. Mehenti (12/14/06) Message-ID: <6.2.1.2.2.20061207004058.04d78230@nmehenti.pobox.stanford.edu> PH.D. ORAL EXAMINATION "NOVEL INTERFACES FOR BIOMIMETIC RETINAL PROSTHESES" Neville Z. Mehenti Department of Chemical Engineering, Stanford University Date: Thursday, December 14, 2006 Time: 2:00 pm (Refreshments at 1:45 pm) Place: Center for Integrated Systems, CIS-X 101 Abstract Retinal prostheses, usually in the form of a planar microelectrode array, are being developed to restore vision to patients suffering from retinal degenerations, such as age-related macular degeneration and retinitis pigmentosa. Both diseases result in the irreversible deterioration of photoreceptors in the sensory retina, but cell layers within the neural retina remain relatively intact and excitable. While results are encouraging from current prostheses, which electrically stimulate groups of these neurons, numerous challenges remain before retinal prosthetic devices can produce useful vision. This thesis work addresses some of the challenges. The first part of this thesis focuses on applying micropatterning technologies to direct neuronal growth to individual electrodes for single cell stimulation. Microcontact printing (?CP) was applied to align and pattern laminin across a microelectrode array, over which retinal ganglion cells (RGCs) were seeded and extended discrete neurites along the pattern to individual electrodes. The stimulation threshold currents of RGCs micropatterned to electrodes were found to be significantly less than those of non-patterned RGCs over a wide range of electrode-soma distances, as determined with calcium imaging techniques. Moreover, the stimulation threshold for micropatterned cells was found to be independent of electrode-soma distance, and there was no significant effect of ?CP on cell excitability. The stimulation results quantitatively demonstrate the potential benefits of a retinal prosthetic interface based on directed neuronal growth. The second portion of this thesis presents a flexible microfluidic device that actuates neurotransmitter release for localized cell stimulation. The device is based on a polymer membrane with an aperture, through which the selective release of chemical pulses is controlled by microfluidic switching in an underlying channel network. The chemical release properties have been characterized using fluorescence microscopy as a function of pulse frequency and duration. Hippocampal neurons were cultured on the microdevices, and it was shown that the glutamate release properties could be tuned to repeatedly elicit discrete action potentials in cells seeded proximate to the aperture, including single cell stimulation at 2 Hz. The results establish the feasibility of a prosthetic interface based on localized neurotransmitter delivery to achieve safe and repeatable neuron stimulation. This thesis addresses key limitations of current retinal prostheses by engineering interfaces that achieve high-resolution and physiological cell stimulation, and thus potentially useful vision. The development of these novel technologies may provide the biomimetic approach that is necessary not only to treat retinal degenerations, but a variety of neurological disorders as well. From mahnaz at stanford.edu Fri Dec 8 15:58:48 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 08 Dec 2006 15:58:48 -0800 Subject: SVGrack Message-ID: <4579FC38.1020004@stanford.edu> Hello all, I need you to remove your wafer boxes and notebooks from the top of the rack next to SVGcoater. The spot belongs to EE410 so please help me by removing your stuff. mahnaz From mtang at stanford.edu Fri Dec 8 16:04:00 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 08 Dec 2006 16:04:00 -0800 Subject: Reminder (and Clarification) of Lab Cleanup - Dec. 11-19 Message-ID: <4579FD70.5020003@stanford.edu> Hi everyone -- Reminder of the annual lab cleanup, to start next week; for details, see: http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:2532:200612:pghhonkddkomoaagepck A couple of clarifications. First, the RED DOTS on personal items indicate that will be allowed in the lab ONLY UNTIL SHUTDOWN. At 7 am on Dec. 18, EVERYTHING left in the lab outside of personal bins will be removed, whether or not there's a RED DOT on it. (The RED DOT is only a temporary reprieve.) So please make sure to remove any personal items left outside of personal bins before shutdown. Second, any personal chemicals must have the current date. Chemicals with no date labels or dates before 2006 will be removed. If you want to keep an old bottle in the lab, please re-date it. Many apologies for any confusion. With your help, things will be much neater and cleaner when you return in the new year. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From rohank at stanford.edu Mon Dec 11 16:29:47 2006 From: rohank at stanford.edu (Rohan D. Kekatpure) Date: Mon, 11 Dec 2006 16:29:47 -0800 (PST) Subject: Thermal reflow of +ve resist 3612 Message-ID: Dear Labmembers, I am using a process in which I expose circular patterns in the 1 um thick 3612 resist using Nikon stepper. I am concerned about the circularity and the line edge roughness in the resist (which I intend to use as a dry etch mask). Therefore, I am wondering if anyone has tried a reflow on this particular resist. If indeed you have tried, it would be great if you could provide me the starting parameters (reflow temperature and time). Thanks in advance for your help. -Rohan From jimkruger at yahoo.com Tue Dec 12 09:45:49 2006 From: jimkruger at yahoo.com (jim kruger) Date: Tue, 12 Dec 2006 09:45:49 -0800 (PST) Subject: Thermal reflow of +ve resist 3612 In-Reply-To: Message-ID: <181244.74757.qm@web38910.mail.mud.yahoo.com> I do not have a complete recipe for you, but I have found that about 15 minutes in the EEprom eraser (the old DUV cure sytem near EV-Align) followed by about 5 minutes on a 200C hotplate will cross-link 3612 without too much change in small features. Larger features (the edge or corner of a big block of resist) show some fringes, indicating a change of thickness at the edge, but I believe the resist edge at the substrate is not moving. Adjusting the UV time and the hotplate temperature might give the smoothing you desire. I use this recipe to prevent mixing of a second layer of resist so I can add patterns with a different mask. The cured resist will withstand a short (few second spray) of acetone, I have not tried a long acetone soak. It is OK in the developer for the second resist. Another technique for edge smoothing is to use a low pressure O2 plasma descum to remove 5 or 10% of the resist selectively to the substrate before the substrate etch. This can be combined with the UV + hotplate as modified from the recipe above. What are you etching in which system/recipe? Selectivity to resist? jim --- "Rohan D. Kekatpure" wrote: > Dear Labmembers, > > I am using a process in which I expose circular > patterns in the 1 um thick > 3612 resist using Nikon stepper. I am concerned > about the circularity and > the line edge roughness in the resist (which I > intend to use as a dry > etch mask). Therefore, I am wondering if anyone has > tried a reflow on this > particular resist. If indeed you have tried, it > would be great if you > could provide me the starting parameters (reflow > temperature and time). > > Thanks in advance for your help. > > -Rohan > > > __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From mbaran at stanford.edu Tue Dec 12 10:09:36 2006 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 12 Dec 2006 10:09:36 -0800 Subject: Found Motorola Pagenet Pager Outside the Lab Message-ID: <20061212180936.9ABE14C5F8@smtp3.stanford.edu> Dear Labmembers, If you are wondering why you haven't received a page lately or you think you're having a quiet day please check to see that you still have your pager on. A Motorola Pagenet Pager was found outside the lab so, this might be yours. I now, have it at my desk waiting for you to pick it up. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rcrane at snf.stanford.edu Tue Dec 12 14:12:26 2006 From: rcrane at snf.stanford.edu (Dick Crane) Date: Tue, 12 Dec 2006 14:12:26 -0800 Subject: Holiday shutdown Message-ID: <457F294A.9060702@snf.stanford.edu> CIS/CISX and lab dwellers, It is time for the annual holiday shutdown. CIS and CISX buildings will be locked and heating turned off from 5:00 PM, Tuesday, 12/19/06 until 6:00 AM, Tuesday, 1/2/07. US mail, campus mail and delivery services (UPS, FedEx, etc.) will not be available during the shutdown. CIS receiving yard will be closed and locked. Please do not unlock or prop open outside doors. There will be a building wide emergency electrical power test, which will include a 10 second, emergency power shutdown during transfer, some time from 0730 to 1200 on Monday, 12/18/06. Please plan accordingly (emergency power outlets have red cover plates). The CISX and CIS exhaust scrubber systems will be off-line from 0700, 12/20/06 through 1600, 12/21/06. Please remove and/or cover fume producing sources which are exhausted (fume hoods). All toxic and flammable gases will be shut down from 0700, 12/18/06 through 1600, 1/2/07. All acid waste drains will be shut down from 0700, 12/21/06 through 1600, 12/12/06. Summary: Building locked from 1700, 12/19/06 to 0600 -1/2/07. Building heat off from 12/19/06 -1/2/07. Emergency electrical power disruptions 12/18/06, from 0700 -1200. Fume exhaust off from 0700, 12/20/06 to 1600 -12/21/06. No mail or delivery services 12/19/06 -1/2/07. All toxic and flammable gases off from 0700, 12/18/06 - 1600, 1/2/07. All acid waste drains off from 0700, 12/21/06 - 1600, 12/12/06 Thanks and have a pleasant holiday, Dick 5-3665 From vossough at memswork.net Tue Dec 12 14:48:59 2006 From: vossough at memswork.net (Kris) Date: Tue, 12 Dec 2006 14:48:59 -0800 (PST) Subject: Missing mask......... Message-ID: <37949.37257.qm@web54102.mail.yahoo.com> We are missing a five inch mask made by Compugraphics (red box). Last I saw it was around August-September. The name on the mask is "Nano and MicroTechnology Consultants" and the layer is "AA". It is a dark field mask with small patterns on only the left side (Cr up), so it may be easy to mistake it for a Cr plate. Please let me know if you find it. Thanks, --Kris K. Vossough, Ph.D. Nano and Micro Technology Consultants E-mail: vossough at memswork.net Voice: (408)373-5413 Fax: (650)798-5001 http://www.memswork.net ____________________________________________________________________________________ Do you Yahoo!? Everyone is raving about the all-new Yahoo! Mail beta. http://new.mail.yahoo.com From jonroth at stanford.edu Tue Dec 12 22:28:02 2006 From: jonroth at stanford.edu (Jonathan Edgar Roth) Date: Tue, 12 Dec 2006 22:28:02 -0800 Subject: PMMA for gluing wafers Message-ID: <1165991282.457f9d7277db0@webmail.stanford.edu> Hi, Do any labmembers have experience using PMMA to glue together two wafers? I was told this is possible, and I'd like to hear if anyone has a recipe. I would like to be able to specify the thickness of the bond. My first guess would be to assume that the bond thickness would be the same as the thickness of the film spun onto a single wafer, though if it's necessary to clamp the wafers for good adhesion this might not be true. I'm also not sure if I should heat the wafers to cure the bond or allow it to dry at room temperature. I'd appreciate your advice. Thanks, Jon From ryantu at stanford.edu Wed Dec 13 09:06:08 2006 From: ryantu at stanford.edu (Ryan Tu) Date: Wed, 13 Dec 2006 09:06:08 -0800 Subject: Ph.D. Oral Examination - Ryan Tu - Dec. 19, 2006 11:00 am Message-ID: PH.D. ORAL EXAMINATION "GERMANIUM NANOWIRE CONTROLLED SYNTHESIS, ALIGNMENT, AND FIELD EFFECT TRANSISTOR PROPERTIES" Ryan Tu Department of Materials Science and Engineering, Stanford University Advisors: Hongjie Dai, Yoshio Nishi, and James Gibbons Date: Tuesday, Dec. 19, 2006 11:00 am Location: CIS-X 101 (Refreshment will be served at 10:45 am) Abstract Much excitement has been generated in recent years about semiconductor nanowires (NWs) for future high performance electronics. Single crystal NWs with diameters ranging from 5nm to 50nm can be chemically synthesized with relative ease; thus allowing the opportunity for bottom-up fabrication of NW-based integrated circuits. Furthermore, the cylindrical symmetry of NWs offers an advantage over top-down lithographically patterned circuits for the realization of surround-gated structures to minimize short channel effects. As we near the end of the ITRS roadmap at a point where continued reductions in length scales are unable to surmount the fundamental limitations of silicon, germanium (Ge) has gained renew interest as a choice of materials for future electronics owing to its high hole and electron mobility. Combining both the structural symmetry of NWs and the high mobility of Ge, GeNW-based devices have the potential to address future device scaling limitations. In this thesis defense, I review the electrical properties and discuss the first direct gate capacitance measurements of various GeNW-based field effect transistors (FETs). Single crystalline GeNWs were synthesized via the vapor-liquid-solid mechanism at a low temperature of 275?C from gold nanoparticles. Several methods were developed to control the registry, orientation, and pitch of GeNW arrays, including an e-beam lithography method to form arrays of individual 20nm gold nanoparticles followed by 100% yield synthesis and a flow alignment method to deposit thin films of aligned nanowires with controlled density. Depletion mode GeNW FETs with Schottky source-drain metal contacts were fabricated on top of thermally oxidized silicon substrates with back-gated, top-gated, and surround-gated geometries. An atomic layer deposition process for HfO2 and Al2O3 was developed to form the gate oxide in top-gated and surround-gated devices. C-V curves of disk capacitors fabricated on planar Ge substrates treated with various surface layer nitridation and silicon interlayer deposition processes were analyzed to reduce hysteresis and the density of interface states. A novel method for measuring atto-farads of capacitance was developed and used to measure gate capacitance in individual top-gated and surround-gated GeNW FETs. This direct measurement enabled the first accurate evaluation of hole mobility ~400cm2/Vs in GeNWs. 2D finite element simulations with carefully measured oxide thicknesses and dielectric constants shed light into the validity of using such approximations in mobility calculations. Optimized surround-gated GeNW FETs exhibited high saturation current and capacitance per unit length with subthreshold slope ~100mV/dec, and could potentially be one component of future high mobility nanowire integrated circuits. -------------- next part -------------- A non-text attachment was scrubbed... Name: Abstract.pdf Type: application/octet-stream Size: 70540 bytes Desc: not available URL: From nmehenti at stanford.edu Wed Dec 13 15:16:19 2006 From: nmehenti at stanford.edu (Neville Mehenti) Date: Wed, 13 Dec 2006 15:16:19 -0800 Subject: Ph.D. Oral Examination -- Neville Z. Mehenti (Thursday, 12/14) Message-ID: <6.2.1.2.2.20061213151447.050c3400@nmehenti.pobox.stanford.edu> PH.D. ORAL EXAMINATION "NOVEL INTERFACES FOR BIOMIMETIC RETINAL PROSTHESES" Neville Z. Mehenti Department of Chemical Engineering, Stanford University Date: Thursday, December 14, 2006 Time: 2:00 pm (Refreshments at 1:45 pm) Place: Center for Integrated Systems, CIS-X 101 Abstract Retinal prostheses, usually in the form of a planar microelectrode array, are being developed to restore vision to patients suffering from retinal degenerations, such as age-related macular degeneration and retinitis pigmentosa. Both diseases result in the irreversible deterioration of photoreceptors in the sensory retina, but cell layers within the neural retina remain relatively intact and excitable. While results are encouraging from current prostheses, which electrically stimulate groups of these neurons, numerous challenges remain before retinal prosthetic devices can produce useful vision. This thesis work addresses some of the challenges. The first part of this thesis focuses on applying micropatterning technologies to direct neuronal growth to individual electrodes for single cell stimulation. Microcontact printing (?CP) was applied to align and pattern laminin across a microelectrode array, over which retinal ganglion cells (RGCs) were seeded and extended discrete neurites along the pattern to individual electrodes. The stimulation threshold currents of RGCs micropatterned to electrodes were found to be significantly less than those of non-patterned RGCs over a wide range of electrode-soma distances, as determined with calcium imaging techniques. Moreover, the stimulation threshold for micropatterned cells was found to be independent of electrode-soma distance, and there was no significant effect of ?CP on cell excitability. The stimulation results quantitatively demonstrate the potential benefits of a retinal prosthetic interface based on directed neuronal growth. The second portion of this thesis presents a flexible microfluidic device that actuates neurotransmitter release for localized cell stimulation. The device is based on a polymer membrane with an aperture, through which the selective release of chemical pulses is controlled by microfluidic switching in an underlying channel network. The chemical release properties have been characterized using fluorescence microscopy as a function of pulse frequency and duration. Hippocampal neurons were cultured on the microdevices, and it was shown that the glutamate release properties could be tuned to repeatedly elicit discrete action potentials in cells seeded proximate to the aperture, including single cell stimulation at 2 Hz. The results establish the feasibility of a prosthetic interface based on localized neurotransmitter delivery to achieve safe and repeatable neuron stimulation. This thesis addresses key limitations of current retinal prostheses by engineering interfaces that achieve high-resolution and physiological cell stimulation, and thus potentially useful vision. The development of these novel technologies may provide the biomimetic approach that is necessary not only to treat retinal degenerations, but a variety of neurological disorders as well. From sjo at stanford.edu Wed Dec 13 16:33:51 2006 From: sjo at stanford.edu (Sebastian J. Osterfeld) Date: Wed, 13 Dec 2006 16:33:51 -0800 Subject: Non-alkaline developer/resist for photolithography ? Message-ID: <45809BEF.4030009@stanford.edu> Dear Labmembers, I am looking for a purely solvent-based photoresist/developer combination, so that the fragile spin valves (magnetoresistive sensors) on my wafer are not exposed to the alkaline developer LDD26W, which can severely corrode their very fine and essential copper layer. LDD26W etches Aluminum at a rate of roughly 30 nm per minute, and copper even faster - once when I tried to make a copper hard mask, the LDD26W literally tore through the copper film even before the resist development was complete. I need to fabricate metallic leads for these copper-film containing spin valves by means of a lift-off process, and where these leads overlap with the sensors, the opening in the resist exposes the sensors to the developer, quite possibly damaging them in the process. This may be a concern especially for submicron sensors - the smaller the sensors, the shorter the time they can withstand immersion in a corrosive environment. On the other hand, the required feature size is quite lenient - 2 micron should suffice for the lead mask. This means a "coarse" process or resist would be o.k. In summary: - Solvent-based resist & developer for optical photolithography - Avoids alkaline or corrosive aqueous solutions - Suitable for lift-off of up to 300 nm metal (bilayer if possible) - Coarse resolution (cd = 2 microns) is o.k. Please let me know if you have a working recipe. Thanks! -- Sebastian J. Osterfeld PhD. Student / Shan X. Wang Group Dept. of Materials Science & Engineering From shott at stanford.edu Wed Dec 13 18:51:56 2006 From: shott at stanford.edu (John Shott) Date: Wed, 13 Dec 2006 18:51:56 -0800 Subject: Acid Waste Neutralization system OK! Message-ID: <4580BC4C.1020706@stanford.edu> SNF Lab Members: At a bit before 5 p.m. this evening, the yellow "Acid Neutralization Failure" lamps began flashing. There was a temporary "Do Not Dump Acid" sign placed on the door at that point. At this time (about 6:45 p.m.), we believe that the acid waste system is fully operational. Tony Padilla got the call from work control and was back here before 5:30. A little investigation showed that the "fine tune" pumps that inject sodium hydroxide into the system had lost their prime. Some more work followed by some testing restored the prime to the pumps and verified that the system is functioning properly. Accordingly, it is now OK to dump acids in the normal, safe manner. Thank you for your continued support, John From xzhuang at stanford.edu Thu Dec 14 12:28:56 2006 From: xzhuang at stanford.edu (Steve Zhuang) Date: Thu, 14 Dec 2006 12:28:56 -0800 Subject: question on pad etch Message-ID: <1166128136.4581b40845d8b@webmail.stanford.edu> Dear lab members, I have a question on Pad Etch. I want to use it to etch LTO. In my case, the LTO is on top of a layer of Al/Ti. Does pad etch attach Al or Ti? Your input is highly appreciated. Thanks Steve Zhuang PhD student Khuri-Yakub Group From mtang at stanford.edu Fri Dec 15 10:22:31 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 15 Dec 2006 10:22:31 -0800 Subject: Annual Building Holiday Party - Today! (Friday, 2 pm) Message-ID: <4582E7E7.5040506@stanford.edu> Hi everyone! Come and join your building and labmates for the annual holiday party! Food and games start at 2 pm, in the CIS hallway. Here's a chance to win your very own 12" wafer. Hope to see you all there! The CIS and SNF Staff From hweiyin at stanford.edu Sat Dec 16 13:53:59 2006 From: hweiyin at stanford.edu (Serene Koh) Date: Sat, 16 Dec 2006 13:53:59 -0800 (PST) Subject: Note: no more 50:1 HF in chemical passthrough Message-ID: Hi, I just used the last bottle of 50:1 HF in the chemical passthrough. - Serene From shott at stanford.edu Sun Dec 17 08:47:25 2006 From: shott at stanford.edu (John Shott) Date: Sun, 17 Dec 2006 08:47:25 -0800 Subject: 50:1 HF and friends restocked ... Message-ID: <4585749D.2000602@stanford.edu> An HTML attachment was scrubbed... URL: From ryantu at stanford.edu Mon Dec 18 11:17:16 2006 From: ryantu at stanford.edu (Ryan Tu) Date: Mon, 18 Dec 2006 11:17:16 -0800 Subject: Reminder: Ph.D. Oral Examination - Ryan Tu - Dec. 19, 2006 11:00 am In-Reply-To: Message-ID: > PH.D. ORAL EXAMINATION > > "GERMANIUM NANOWIRE CONTROLLED SYNTHESIS, ALIGNMENT, AND FIELD EFFECT > TRANSISTOR PROPERTIES" > > Ryan Tu > Department of Materials Science and Engineering, Stanford University > Advisors: Hongjie Dai, Yoshio Nishi, and James Gibbons > > Date: Tuesday, Dec. 19, 2006 11:00 am > Location: CIS-X 101 > (Refreshment will be served at 10:45 am) > > > Abstract > > Much excitement has been generated in recent years about semiconductor > nanowires (NWs) for future high performance electronics. Single crystal NWs > with diameters ranging from 5nm to 50nm can be chemically synthesized with > relative ease; thus allowing the opportunity for bottom-up fabrication of > NW-based integrated circuits. Furthermore, the cylindrical symmetry of NWs > offers an advantage over top-down lithographically patterned circuits for > the realization of surround-gated structures to minimize short channel > effects. As we near the end of the ITRS roadmap at a point where continued > reductions in length scales are unable to surmount the fundamental > limitations of silicon, germanium (Ge) has gained renew interest as a choice > of materials for future electronics owing to its high hole and electron > mobility. Combining both the structural symmetry of NWs and the high > mobility of Ge, GeNW-based devices have the potential to address future > device scaling limitations. > > In this thesis defense, I review the electrical properties and discuss the > first direct gate capacitance measurements of various GeNW-based field > effect transistors (FETs). Single crystalline GeNWs were synthesized via > the vapor-liquid-solid mechanism at a low temperature of 275?C from gold > nanoparticles. Several methods were developed to control the registry, > orientation, and pitch of GeNW arrays, including an e-beam lithography > method to form arrays of individual 20nm gold nanoparticles followed by 100% > yield synthesis and a flow alignment method to deposit thin films of aligned > nanowires with controlled density. Depletion mode GeNW FETs with Schottky > source-drain metal contacts were fabricated on top of thermally oxidized > silicon substrates with back-gated, top-gated, and surround-gated > geometries. An atomic layer deposition process for HfO2 and Al2O3 was > developed to form the gate oxide in top-gated and surround-gated devices. > C-V curves of disk capacitors fabricated on planar Ge substrates treated > with various surface layer nitridation and silicon interlayer deposition > processes were analyzed to reduce hysteresis and the density of interface > states. A novel method for measuring atto-farads of capacitance was > developed and used to measure gate capacitance in individual top-gated and > surround-gated GeNW FETs. This direct measurement enabled the first > accurate evaluation of hole mobility ~400cm2/Vs in GeNWs. 2D finite element > simulations with carefully measured oxide thicknesses and dielectric > constants shed light into the validity of using such approximations in > mobility calculations. Optimized surround-gated GeNW FETs exhibited high > saturation current and capacitance per unit length with subthreshold slope > ~100mV/dec, and could potentially be one component of future high mobility > nanowire integrated circuits. >