Fw: Please forward the notice of Toshiba-Stanford day to CIS mailing list

[Ying Chen]

----- Original Message ----- 
From: "Atsuhiro Kinoshita" <atsuhiro.kinoshita at toshiba.co.jp>
To: <mihuhou at stanford.edu>
Sent: Tuesday, December 05, 2006 5:26 PM
Subject: Please forward the notice of Toshiba-Stanford day to CIS mailing
list


> Dear CIS Faculty Members and Students,
>
> Toshiba-Stanford Day will be held at CIS-X auditorium on
> December 15, 2006, in order to introduce Toshiba technologies
> to CIS members and to enhance the relationship between
> Toshiba and Stanford University.
>
> We, Toshiba, will present 9 papers. The papers will be discussing
> state-of-the-art TOSHIBA technologies as well as physical
> mechanisms behind present/future MOSFETs. All the papers
> are based on IEDM 2006 presentations.
> Several managers at Toshiba Corporation will also attend the
> events.
> In addition, Stanford professors will present recent research
> topics at Stanford University.
>
> Every CIS faculty members and students are very welcome to join
> this event.
>
> RSVP to Gabrielle Scofield via email at: gabrielles at ee.stanford.edu
>
>
> ---------------------------------------------------------------------
>
> Toshiba-Stanford Day
> CISX Auditorium, December 15, 2006
>
> 8:30 am Breakfast
>
> Session I: Introduction (9:00am-9:30am)
>
> 9:00 am Introduction
>   Professor Yoshio Nishi, Stanford University, & Noburu Fukushima, TOSHIBA
> 9:15 am Overview of TOSHIBA R&D Activities on Advanced LSI Technologies
>   Akira Nishiyama, TOSHIBA
>
> Session II: Advanced MOSFETs (9:30pm-12:30pm)
>
> 9:30 am Recent Research Topics on High Mobility Channels in Stanford
> University
>   Professor Krishna C. Saraswat, Stanford University
> 10:00 am Comprehensive Study on Injection Velocity Enhancement in
> Dopant-Segregated Schottky MOSFETs
>   Atsuhiro Kinoshita, TOSHIBA
> 10:30 am Coffee Break
> 11:00 am 1 nm NiSi/Si Junction Design based on First-Principles
> Calculation for Ultimately Low Contact Resistance
>   Takashi Yamauchi, TOSHIBA
> 11:30 am Guideline for Low Temperature Operation Technique to Extend
> CMOS Scaling s
>   Akira Hokazono, TOSHIBA
> 12:00 pm A 45nm High Performance Bulk Logic Platform Technology (CMOS6)
> using Ultra High NA(1.07) Immersion Lithography with Hybrid
> Dual-Damascene Structure and Porous Low-k BEOL
>   Hideaki Nii, TOSHIBA
> 12:30 pm Lunch
>
> Session III: Advanced Gate Stack & Others (2:00pm-5:20pm)
>
> 2:00 pm Recent Research Topics on High-k and Metal Gates in Stanford
> University
>   Paul C. McIntyre, Stanford University
> 2:30 pm Impact of Very Low Hf concentration (Hf=6%) Cap Layer on
> Performance and Reliability Improvement of HfSiON -CMOSFET with EOT
> scalable to 1nm
>   Motoyuki Satoh, TOSHIBA
> 3:00 pm Practical Work Function Tuning Based on Physical and Chemical
> Nature of Interfacial Impurity in Ni-FUSI/SiON and HfSiON systems
>   Yoshinori Tsuchiya, TOSHIBA
> 3:30 pm Coffee Break
> 4:00 pm Universal Relationship between Low-Field Mobility and High-Field
> Carrier Velocity in High-k and SiO2 Gate Dielectric MOSFETs
>   Masumi Saitoh, TOSHIBA
> 4:30 pm Carrier Transport in (110) nMOSFETs: Subband Structures,
> Non-Parabolicity, Mobility Characteristics, and Uniaxial Stress
Engineering
>   Ken Uchida, TOSHIBA
> 4:50 pm Floating Body RAM Technology and its Scalability to 32nm Node
> and Beyond
>   Tomoaki Shino, TOSHIBA
> 5:20 pm Closing Remarks & Adjourn
> Professor Nishi, Stanford University, & Noburu Fukushima, TOSHIBA
>
> ---------------------------------------------------------------------