Reminder: Ph.D. Oral Defense Announcement--Tomorrow Dec. 7 10:00 Packard 101--Hoyeol Cho

Hoyeol Cho hoyeolcho at
Wed Dec 6 12:29:59 PST 2006

*Performance Comparison between Copper, Carbon Nanotube, and Optics for
Off-chip and On-chip Interconnects*

Ph.D. Candidate: Hoyeol Cho

Advisor: Krishna C. Saraswat

Date: Thursday, Dec. 7, 2006 10:00 am

Location: Packard 101 (Refreshment will be served at 9:45 am )

*Abstract *– For more than 30 years, the performance of silicon integrated
circuits has improved at an astonishing rate. The number of functions per
chip has grown exponentially, dramatically bringing down the cost per
function. However, for the first time the relentless scaling paradigm is
threatened by fundamental limits including excessive power dissipation,
insufficient communication bandwidth and signal latency. Many of these
obstacles stem from the physical limitation of Cu-based electrical wires,
making it imperative to examine alternate interconnect schemes for future
ICs. The two most important novel potential candidates are optical and
carbon nanotube (CNT)-based interconnects.

Optical interconnect due to its high bandwidth, low signal attenuation and
cross talk, is an ideal candidate to tackle the challenges imposed by
electrical wiring for both off-chip and possibly on-chip application.
Because the modern ICs require an ever-increasing system bandwidth and have
a large power density, a realistic study of performance comparison between
electrical and optical interconnects is of paramount importance. In
addition, such a comparison framework aids in setting clear goals on the
requirements of opto-electronic devices to deliver a superior performance
than their electrical counterparts. For on-chip application, o ptical
interconnects can potentially reduce latency, provide high-bandwidth at
relatively low power. However, an optical waveguide, has a relatively larger
size (pitch~0.6 m m), making it difficult to provide high bandwidth density.
This can be mitigated using wavelength division multiplexing (WDM). CNT
interconnects, on the other hand, have the flexibility of being implemented
in the same size scale as the existing Cu on-chip wires, hence possibly can
provide high bandwidth density. In addition they have the advantage of
having a large electron mean free path, hence low resistance. This can
result in low latency compared to Cu/low-K counterpart.

In this talk, for on-chip application, we compare CNT and optical
interconnects with Cu interconnects using both commonly used metrics:
latency and power and a compound metric which captures system requirements
more efficiently. The necessity of compound metrics is motivated by the fact
that larger bandwidth and a smaller latency can be obtained using more area
resources. Hence area normalization is necessary. In addition, the total
power budget can also be used to increase the aggregate bandwidth, making
power normalization also imperative. Hence, we use bandwidth
density/latency/power as our compound metric. In the future, because of
multi-core architecture, the designers care about the bandwidth density,
latency and power dissipation of global communication. We extensively
examine the impact of device parameters-modulator and detector capacitances
for optics, materials parameters-mean free path and packing density for
CNTs, and system parameters-global clock frequency and switching activity on
both commonly used and the compound metrics. We find that at 22nm technology
node small detector and modulator capacitances for optical interconnects
(~10fF) yields superior, at least comparable, performance with CNTs
(practical, electron mean free path of 0.9m m) and Cu for greater than 35%
and 20% switching activity, respectively. However, improving mean free path
of CNTs (~2.8 mm) increases this crossover switching activity to 80%.

Finally, for off-chip application, we compare high speed optical and
electrical interconnect using power vs. bandwidth. We find that beyond
critical length, power optimized optical interconnects dissipates lower
power compared to high-speed electrical signaling scheme. Beyond 32nm
technology node with its commensurate bandwidth, optical interconnect
becomes favorable for the distance less than 10cm correspondent to
inter-chip communication. This analysis of the impacts of device/system
parameters on critical length gives system/device designer the evaluation
framework of the performance of the system.
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