Reminder: Ph.D. Oral Examination - Ryan Tu - Dec. 19, 2006 11:00 am

Ryan Tu ryantu at
Mon Dec 18 11:17:16 PST 2006

> Ryan Tu
> Department of Materials Science and Engineering, Stanford University
> Advisors: Hongjie Dai, Yoshio Nishi, and James Gibbons
> Date: Tuesday, Dec. 19, 2006 11:00 am
> Location: CIS-X 101
> (Refreshment will be served at 10:45 am)
> Abstract
> Much excitement has been generated in recent years about semiconductor
> nanowires (NWs) for future high performance electronics. Single crystal NWs
> with diameters ranging from 5nm to 50nm can be chemically synthesized with
> relative ease; thus allowing the opportunity for bottom-up fabrication of
> NW-based integrated circuits.  Furthermore, the cylindrical symmetry of NWs
> offers an advantage over top-down lithographically patterned circuits for
> the realization of surround-gated structures to minimize short channel
> effects.  As we near the end of the ITRS roadmap at a point where continued
> reductions in length scales are unable to surmount the fundamental
> limitations of silicon, germanium (Ge) has gained renew interest as a choice
> of materials for future electronics owing to its high hole and electron
> mobility. Combining both the structural symmetry of NWs and the high
> mobility of Ge, GeNW-based devices have the potential to address future
> device scaling limitations.
> In this thesis defense, I review the electrical properties and discuss the
> first direct gate capacitance measurements of various GeNW-based field
> effect transistors (FETs).  Single crystalline GeNWs were synthesized via
> the vapor-liquid-solid mechanism at a low temperature of 275°C from gold
> nanoparticles.  Several methods were developed to control the registry,
> orientation, and pitch of GeNW arrays, including an e-beam lithography
> method to form arrays of individual 20nm gold nanoparticles followed by 100%
> yield synthesis and a flow alignment method to deposit thin films of aligned
> nanowires with controlled density.  Depletion mode GeNW FETs with Schottky
> source-drain metal contacts were fabricated on top of thermally oxidized
> silicon substrates with back-gated, top-gated, and surround-gated
> geometries. An atomic layer deposition process for HfO2 and Al2O3 was
> developed to form the gate oxide in top-gated and surround-gated devices.
> C-V curves of disk capacitors fabricated on planar Ge substrates treated
> with various surface layer nitridation and silicon interlayer deposition
> processes were analyzed to reduce hysteresis and the density of interface
> states.  A novel method for measuring atto-farads of capacitance was
> developed and used to measure gate capacitance in individual top-gated and
> surround-gated GeNW FETs.  This direct measurement enabled the first
> accurate evaluation of hole mobility ~400cm2/Vs in GeNWs. 2D finite element
> simulations with carefully measured oxide thicknesses and dielectric
> constants shed light into the validity of using such approximations in
> mobility calculations.  Optimized surround-gated GeNW FETs exhibited high
> saturation current and capacitance per unit length with subthreshold slope
> ~100mV/dec, and could potentially be one component of future high mobility
> nanowire integrated circuits.

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