From fely at gloworm.Stanford.EDU Wed Feb 1 09:08:09 2006 From: fely at gloworm.Stanford.EDU (Fely Barrera) Date: Wed, 01 Feb 2006 09:08:09 -0800 Subject: EE 310 Seminar, February 7, 2006 Message-ID: <200602011708.k11H89OQ016886@gloworm.Stanford.EDU> Title: Colloidal Nanocrystals: Single Electron Transport and Self Assembly Date: Feb 7, 2006 (Tuesday) Time: 4:15 pm - 5:05 pm Place: Hewlett 102 Speaker: Yi Cui Assistant Professor Department of Materials Science and Engineering Stanford University Colloidal nanocrystals represent an important type of nanomaterials for electronics, photonics and energy conversion. Understanding the electronic coupling characteristics of self-assembled nanocrystal materials is essential for these applications. Here I present my recent research in studying coupling in different forms of self-assembled nanocrystal systems. First, semiconductor nanotetrapods are unique self-assembled systems of quantum dots and rods. I have demonstrated by single electron transistor measurements that either ionic or covalent bonding-type of coupling can exist when the interaction between the quantum dot at the junction and the arm rods is weak or strong, respectively. Second, I have developed a facile fluidic method for organizing nanocrystals into large-scale device arrays, which incorporates a controlled number of nanocrystals at lithographically precise locations on a chip and within a circuit. The method provides interesting systems for studying chemic! ally-tunable coupling phenomena. Biography: Yi Cui went to University of Science and Technology of China, where he received a Bachelor's degree in Chemistry in 1998. He attended graduate school from 1998 to 2002 at Harvard University, where he worked under supervision of Professor Charles M. Lieber. His Ph.D thesis concerned semiconductor nanowires for nanotechnology including synthesis, nanoelectroncis and nanosensor applications. After that, he went on to work as a Miller Postdoctoral Fellow with Professor Paul Alivisatos at University of California, Berkeley and Ernest Orlando Lawrence Berkeley National Laboratory until now. His postdoctoral work was mainly on electronics and assembly using colloidal nanocrystals. He is now an Assistant Professor in Department of Materials Science and Engineering at Stanford University. His current research is focused on nanomaterials synthesis, electronic properties, memory and sensor devices. He has received the Technology Review World Top Young Innovator Award (2004), Miller Research Fellowship (2003), Distinguished Graduate Student Award in Nanotechnology (Foresight Institute, 2002), Gold Medal of Graduate Student Award (Material Research Society, 2001). From xzhuang at stanford.edu Wed Feb 1 13:53:53 2006 From: xzhuang at stanford.edu (Steve Zhuang) Date: Wed, 1 Feb 2006 13:53:53 -0800 Subject: spin coating teflon References: <005001c626d4$018ae580$6401a8c0@minicat> Message-ID: <02cd01c62779$fe43a550$bb5640ab@pky7> Fabless Business Model for EntrepreneursDear Labmembers, I'm just wondering if anyone has experience with spin coating teflon on a silicon or oxide surface? I'm curious how the adhesion of the spin coated teflon is to these surfaces. Any input will be highly appreciated! Cheers Steve Zhuang K-Y group -------------- next part -------------- An HTML attachment was scrubbed... URL: From shabbir.bashar at nlight.net Fri Feb 3 13:56:27 2006 From: shabbir.bashar at nlight.net (shabbir.bashar) Date: Fri, 3 Feb 2006 13:56:27 -0800 Subject: Sputtered SiO2 Message-ID: <2DB307563B57074B9FDB3B4ABDAB1D6F015321FA@nli-mail2-svr.nlightphotonics.com> Eric, Do you know some place where i can get SiO2 sputter deposited on InP wafers? It needs to be a good electrical isolator and an AR coating ... Thanks! ================= Shabbir A. Bashar, PhD nLight Photonics Corp. 5408 NE 88th Street, Bldg. E Vancouver, WA 98665 Cell: +1 510 386 7304 Office: +1 360 713 5145 Fax: +1 360 546 1960 E-mail: Shabbir.Bashar at nLight.net Web: www.nLight.net Notice: The information in this electronic transmission may contain confidential or legally privileged information and is intended solely for the individual(s) named above. If you are not an intended recipient or an authorized agent, you are hereby notified that reading, distributing, or otherwise disseminating, copying or taking any action based on the contents of this transmission is strictly prohibited. Any unauthorized interception of this transmission is illegal under law. If you have received this transmission in error, please notify the sender then destroy all electronic and print copies of this transmission. The data contained herein may contain EXPORT CONTROLLED information. This message (including any attachments) may contain information which is export controlled and is limited in distribution to authorized persons. If in doubt, please contact the nLight Technology Security Officer at 360-566-4471. -------------- next part -------------- An HTML attachment was scrubbed... URL: From James.Q.Liu at jdsu.com Fri Feb 3 15:12:52 2006 From: James.Q.Liu at jdsu.com (James Q. Liu) Date: Fri, 3 Feb 2006 15:12:52 -0800 Subject: Sputtered SiO2 Message-ID: <0FC4C1B93D218E428D20BFCB9424D5D2015DFF25@SJEXCH02.ds.jdsu.net> Hi Shabbir, You can try LGA Films (www.lgafilms.com ). They have magnetron sputtering system. SiO2 is one of the targets they have on hand. They also do ITO. Good luck, James ________________________________ From: shabbir.bashar [mailto:shabbir.bashar at nlight.net] Sent: Friday, February 03, 2006 1:56 PM To: Eric Perozziello Cc: labmembers at snf.stanford.edu; mtang at snf.stanford.edu; latta at snf.stanford.edu Subject: Sputtered SiO2 Eric, Do you know some place where i can get SiO2 sputter deposited on InP wafers? It needs to be a good electrical isolator and an AR coating ... Thanks! ================= Shabbir A. Bashar, PhD nLight Photonics Corp. 5408 NE 88th Street, Bldg. E Vancouver, WA 98665 Cell: +1 510 386 7304 Office: +1 360 713 5145 Fax: +1 360 546 1960 E-mail: Shabbir.Bashar at nLight.net Web: www.nLight.net Notice: The information in this electronic transmission may contain confidential or legally privileged information and is intended solely for the individual(s) named above. If you are not an intended recipient or an authorized agent, you are hereby notified that reading, distributing, or otherwise disseminating, copying or taking any action based on the contents of this transmission is strictly prohibited. Any unauthorized interception of this transmission is illegal under law. If you have received this transmission in error, please notify the sender then destroy all electronic and print copies of this transmission. The data contained herein may contain EXPORT CONTROLLED information. This message (including any attachments) may contain information which is export controlled and is limited in distribution to authorized persons. If in doubt, please contact the nLight Technology Security Officer at 360-566-4471. -------------- next part -------------- An HTML attachment was scrubbed... URL: From kimsora at stanford.edu Mon Feb 6 13:19:14 2006 From: kimsora at stanford.edu (Sora Kim) Date: Mon, 6 Feb 2006 13:19:14 -0800 Subject: Boat with wider slots for tylan1&2? Message-ID: <000d01c62b62$fb7b29a0$325640ab@kimsora> Dear Labmembers, We are looking for somebody who has a boat with wider slots for tylan 1 & 2. We want to bond two wafers together - we put them together and want to aneal them. Please let me know if you have the boat. Thanks! Sora -------------- next part -------------- An HTML attachment was scrubbed... URL: From ahazeghi at stanford.edu Mon Feb 6 22:11:12 2006 From: ahazeghi at stanford.edu (Arash Hazeghi) Date: Mon, 6 Feb 2006 22:11:12 -0800 Subject: Tape Message-ID: Hello, I am looking for a material to tape my samples to a sample holder, the tape must be able to withstand a temperature stress from +273 K to 4K (L He) and it should maintain both good thermal and electrical conductivity, I have heard that silver tapes may be suitable. any suggestions? Thank you, Regards, Arash ------------------------------------------------------------------------ -- Arash Hazeghi PhD Candidate Stanford Center for Integrated Systems, 420 Via Palou Mall, CIS-X 300 tel: 650-725-0418 mobile: 650-353-1866 http://www.stanford.edu/group/nanoelectronics/index.htm From xiangli at stanford.edu Tue Feb 7 01:32:15 2006 From: xiangli at stanford.edu (Xiang Li) Date: Tue, 7 Feb 2006 01:32:15 -0800 Subject: Ph.D Oral Defense (Today): MEMS tunable blazed grating by Xiang Li Message-ID: <1139304735.43e8691f3d931@webmail.stanford.edu> DEPARTMENT OF APPLIED PHYSICS UNIVERSITY PhD DISSERTATION DEFENSE Xiang Li Research Advisor Professor O. Solgaard Design, Fabrication and Applications of MEMS Tunable Blazed Gratings February 7, 2006 @ 1:30 P.M. CIS-X Auditorium, Room 101 ABSTRACT Optical micro-electro-mechanical systems (MEMS) have wide applications in optical telecommunications and display. Blazed gratings on the other hand have been essential components in many optical systems. MEMS tunable blazed gratings that can actuate individual elements of a blazed grating on micrometer level by electrostatic force will not only extend the functionality of convention monolithic blazed gratings with advantages of MEMS, but also enable interesting new applications with its much larger number of degrees of freedom. In my presentation, I will discuss the concept, theory, design, fabrication and applications of MEMS tunable blazed gratings in optical communication and spectroscopy. From guerra at par.stanford.edu Fri Feb 10 10:30:30 2006 From: guerra at par.stanford.edu (Ann Guerra) Date: Fri, 10 Feb 2006 10:30:30 -0800 (PST) Subject: Fujitsu SPECIAL SEMINAR ISSCC06 and discussion Feb. 14 In-Reply-To: References: Message-ID: SPECIAL SEMINAR - AN ISSCC06 PRESENTATION BY FUJITSU and subsequent, afternoon open discussion Tuesday, February 14 10:30 a.m. CIS-101 The Linvill Room "An 18mW, 90-770MHz Synthesizer with Agile Auto-tuning for DTV-tuner Application" Presenter: Masazumi Marutani Abstract An 18 mW, 90-770 MHz, I/Q output synthesizer fabricated in a 0.11 um CMOS process at a supply voltage of 1.2 V. The synthesizer's architecture is optimized to achieve low power and wide-tuning. A divider by 3.5 and 7-bit VCO with an agile auto-tuning block, are included. Phase noise is below -100 dBc/Hz at 100 kHz offset. THEN COME BACK AT 1:30 FOR OPEN DISCUSSION WITH THE FIVE VISITORS FROM FUJITSU From sanjah at stanford.edu Fri Feb 10 13:55:42 2006 From: sanjah at stanford.edu (Sanja Hadzialic) Date: Fri, 10 Feb 2006 13:55:42 -0800 Subject: cmp Message-ID: <1139608542.43ed0bde29521@webmail.stanford.edu> Dear all, Is there anybody who has experience with cmp? We have wafers with poly and thermal oxide which we want to bond, and need to polish them in order to do this. Please let me know if you know where we can do cmp. Thank you! Sanja :~) From wibool at stanford.edu Fri Feb 10 14:14:51 2006 From: wibool at stanford.edu (Wibool Piyawattanametha) Date: Fri, 10 Feb 2006 14:14:51 -0800 Subject: cmp In-Reply-To: <1139608542.43ed0bde29521@webmail.stanford.edu> Message-ID: <000b01c62e8f$6a0b8a20$ed5540ab@IBM2948477BEBC> Try this company: Aptek Industries 414-F Umbarger Road San Jose, CA "Tel: 760 631-0202x22 " "(408) 363-8026 " Fax: 626 744-1919 (408) 363-8529 Wibool Piyawattanametha, Ph.D. Stanford University Departments of Applied Physics, Biological Sciences, and Pediatrics James H. Clark Center (Bio-X) - Room W080 318 Campus Drive Stanford, CA 94305 T: (650) 725-4097 F: (650) 724-5805 -----Original Message----- From: Sanja Hadzialic [mailto:sanjah at stanford.edu] Sent: Friday, February 10, 2006 1:56 PM To: labmembers at snf.stanford.edu Subject: cmp Dear all, Is there anybody who has experience with cmp? We have wafers with poly and thermal oxide which we want to bond, and need to polish them in order to do this. Please let me know if you know where we can do cmp. Thank you! Sanja :~) From Yehiel.Gotkis at kla-tencor.com Fri Feb 10 15:32:25 2006 From: Yehiel.Gotkis at kla-tencor.com (Gotkis, Yehiel) Date: Fri, 10 Feb 2006 15:32:25 -0800 Subject: cmp Message-ID: Vince, I believe guys from the Center of Tribology http://www.cetr.com/ may be able to help Best, Yehiel -----Original Message----- From: vlordi at gmail.com [mailto:vlordi at gmail.com] On Behalf Of Vincenzo Lordi Sent: Friday, February 10, 2006 3:03 PM To: Gotkis, Yehiel Subject: Fwd: cmp Yehiel, Do have any info that might help out this girl at Stanford? She is looking for a place to outsource CMP of poly and oxide on Si. -Vince ---------- Forwarded message ---------- From: Sanja Hadzialic Date: Feb 10, 2006 1:55 PM Subject: cmp To: Dear all, Is there anybody who has experience with cmp? We have wafers with poly and thermal oxide which we want to bond, and need to polish them in order to do this. Please let me know if you know where we can do cmp. Thank you! Sanja :~) From john.wasserbauer at group4labs.com Sat Feb 11 11:40:01 2006 From: john.wasserbauer at group4labs.com (John Wasserbauer) Date: Sat, 11 Feb 2006 11:40:01 -0800 Subject: cmp In-Reply-To: <1139608542.43ed0bde29521@webmail.stanford.edu> Message-ID: <001601c62f42$f51048f0$30a8dd18@Dexter> Hi Sanja, We use Ron Kehl Engineering 384 Umbarger Road San Jose, CA 95111 (408) 629-6632 rkehl at aol.com John Wasserbauer, Ph.D. Group4 Labs 1600 Adams Drive, Suite 112 Menlo Park, CA 94025 -----Original Message----- From: Sanja Hadzialic [mailto:sanjah at stanford.edu] Sent: Friday, February 10, 2006 1:56 PM To: labmembers at snf.stanford.edu Subject: cmp Dear all, Is there anybody who has experience with cmp? We have wafers with poly and thermal oxide which we want to bond, and need to polish them in order to do this. Please let me know if you know where we can do cmp. Thank you! Sanja :~) From jenwang at stanford.edu Mon Feb 13 12:47:07 2006 From: jenwang at stanford.edu (Jen-Shiang Wang) Date: Mon, 13 Feb 2006 12:47:07 -0800 Subject: PhD Oral Defense -- Jen-Shiang Wang Message-ID: <004401c630de$a7625470$0200000a@stanford.edu> Dear lab members, I will have my oral defense presentation this afternoon at 4:15 PM at AP 200 (in Ginzton Lab). I hope to see you there if you happen to have time. Thanks, Jen-Shiang University Ph.D. Oral Examination Jen-Shiang Wang Department of Electrical Engineering, Stanford University Advisor: Prof. Olav Solgaard 4:15 PM, Monday, Feb 13th, AP 200. (Refreshments served at 4:00 PM). ?High-Resolution Optical Maskless Lithography Based on Micromirror Arrays? The increasing cost of photo masks in optical lithography is identified as a key barrier for migrating to sub-100nm features in integrated circuit manufacturing. An economical solution, called optical maskless lithography, has drawn broad interests in the IC industry. In optical maskless lithography, an array of reconfigurable micromirrors replaces the traditional photo mask. Based on their mechanical motion, these micromirrors can be categorized into two groups: tilt mirrors and piston phase-shift mirrors. These two types of mirrors have their own advantages and disadvantages, so the optimal mirror architecture has been a topic of debate over the past few years. We have developed a theoretical model and criteria to evaluate micromirror configuration and verified the model with the simulations (accuracy within ?1.5%). We found that 4-piston mirror is the optimal micromirror configuration, which not only has the capability to generate high-resolution features with strong phase-shift effects, but also has a larger depth of focus and process window in arbitrary pattern generations. Then, I will present an optimal operation strategy for maskless lithography. The strategy utilizes multiple exposures and takes advantage of inherent perfect alignment in maskless lithography system to achieve both high resolutions and large depths of focus. The improvement is verified by an analytic model, and a maximum of 8X improvement in the depth of focus is demonstrated by simulations. Other advantages including relaxing the requirement in the ratio between the minimum feature size and the mirror size, simplifying resolution enhancement, fixing twists in vortex patterns will also be presented. In practice, an array of millions of micromirrors is needed for a high throughput production. To efficiently calibrate such a large number of mirrors, we proposed a method using high sensitive interferometric schemes. The typical sensitivity improvement is about 3X to 4X when the optimized schemes are used. Lastly, I will present the design, process, fabrication, and characterization of an elastomer piston mirror array, or an elastomer spatial light modulator (SLM), that can be scaled to meet the requirements of extreme ultraviolet (EUV- 13nm wavelength) optical maskless lithography. An array of 8-by-7 piston mirrors, a concept-proof device, having a localized piston-motion response with a maximum deflection of 10 nm in an effective area of 14mm-by-14mm will be presented. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Wed Feb 15 15:53:02 2006 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 15 Feb 2006 15:53:02 -0800 Subject: Safety Violation at wbgeneral Message-ID: <43F3BEDE.7040104@snf.stanford.edu> Labmembers -- My apologies for the general broadcast, but the feeling is that the perpetrator just simply cannot be a qualified user at wbgeneral, given the violations (and therefore might not be on the wbgeneral email list.) From the evidence this morning, it would appear that someone used wbgeneral without enabling it and leaving what appears to be ammonium fluoride/BOE crystals in the main sink as well as in spots on the bench. There also appear to be bits of broken glass wafer and tiny flecks of metal everywhere (there are even metal flakes on the N2 gun!) Clearly, no one trained by Uli would have done this (though, as she has pointed out, I covered wbgeneral training in her absence, so can't attest for my trainees.) And if anyone has observed someone using wbgeneral between about 5 pm yesterday and 9 am this morning, please be a good community member and share what you know with your favorite/most-trusted SNF staff member. Thanks for your attention -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mbaran at stanford.edu Thu Feb 16 15:34:52 2006 From: mbaran at stanford.edu (Maureen Baran) Date: Thu, 16 Feb 2006 15:34:52 -0800 Subject: NEC Cell Phone found in Gowning Room Message-ID: <200602162334.k1GNYr7I017975@smtp1.Stanford.EDU> Dear A silver NEC cell phone has been sitting in the Gowning room since this morning. It is now sitting at my desk. If you are missing a cell phone please come and claim it. I am in cubicle # 41 which is closest to the doors facing the Applied Physics building. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From anayfeh at stanford.edu Fri Feb 17 09:55:18 2006 From: anayfeh at stanford.edu (Ammar Munir Nayfeh) Date: Fri, 17 Feb 2006 09:55:18 -0800 (PST) Subject: PhD Orals for Ammar Nayfeh (TODAY) Message-ID: PhD ORALS Department of Electrical Engineering "Heteroepitaxial Growth of Relaxed Germanium on Silicon" Ammar Nayfeh Advisor: Prof. Krishna Saraswat Friday, February 17th 2006 3:45pm (Refreshments served at 3:30pm), CIS-X Auditorium ABSTRACT: Ge is now emerging as a viable candidate to augment Si for CMOS device and optoelectronic applications, making it essential to develop new methods for heteroepitaxial growth of Ge on Si. This is not straightforward due to the large lattice mismatch (4.2%) between Ge and Si, which limits the quality of the heteroepitaxial growth. First, above the critical thickness, misfit dislocations form to relive the stress and subsequently thread to the surface making it unsuitable for any device application. Second, growth of Ge on Si results in island morphology which leads to large surface roughness. We have developed a novel technique to achieve high quality heteroepitaxial Ge layers on Si. The technique involves CVD growth of Ge on Si, followed by in-situ hydrogen annealing with subsequent growth and anneal steps and hence the name Multiple Hydrogen Annealing for Heteroepitaxy (MHAH). Following the first Ge growth and hydrogen annealing, the Ge surface roughness is reduced by 90% to 2.5nm Rrms. An additional CVD Ge layer is grown followed by the final hydrogen annealing. Extensive cross section and plan-view transmission electron microscopy (TEM) imaging was carried out showing that defects are concentrated near the Ge/Si interface. Thus, using the MHAH method we achieved heteroepitaxial-Ge on Si layers with dislocation density as low as 1x10^7cm^-2. An experimentally based theoretical model was developed to explain both the surface roughness reduction and the reduction in dislocation density. As a result, a complete model was formed for the MHAH-Ge growth method. The efficacy of this method is demonstrated by fabricating MOS devices and optical detectors in Ge grown by MHAH. MOS capacitors were fabricated on MHAH Ge layers with negligible hystersis and low Dit, comparable to bulk Ge, using GeOxNy gate dielectrics. Dit was extracted to be asymmetric indicating a possible reason why Ge NMOS mobility is severely degraded. We have also successfully fabricated high-performance Ge p-MOSFETs. The Ge based devices exhibit a peak hole mobility of 250 cm^2/Vs which is 2X larger than Si based PMOS universal mobility. Furthermore, we have demonstrated high-k/metal-gate compatibility using ALD grown Al2O3/Al gate stack. In addition, we have demonstrated the quality of the MHAH-Ge layer by fabricating extremely efficient photo-detectors with minimal dark current. We conclude that MHAH-Ge can be used in achieving heterogeneous integration of a high mobility pure Ge channel transistors and optical devices directly on Si for future technology nodes. In addition, it could be used to fabricate GOI substrates, or for the eventual integration of GaAs/Ge/Si for optoelectronics. From mahnaz at stanford.edu Fri Feb 17 16:48:56 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 17 Feb 2006 16:48:56 -0800 Subject: Yellow cabinets Message-ID: <43F66EF8.8020209@stanford.edu> Hello all, Please follow the labeling of the chemicals in all the yellow cabinets. This morning I found few nonstandard chemical bottles among the SU8 bottles . You may not mix things around. All the nonstandard small chemicals should go to the small yellow cabinet, except all the SU8 chemicals which will be kept on the top shelf of the big yellow cabinet. Follow direction, can not get any easier than it is . Do not give me any opportunity to get rid of your chemicals just because is in the wrong spot. mahnaz From fely at gloworm.Stanford.EDU Tue Feb 21 09:04:11 2006 From: fely at gloworm.Stanford.EDU (Fely Barrera) Date: Tue, 21 Feb 2006 09:04:11 -0800 Subject: EE 310 Seminar, TODAY@4:15 pm Message-ID: <200602211704.k1LH4BjO012913@gloworm.Stanford.EDU> Title: TCAD Modeling of tress-Engineered MOSFETs Speaker:Lee Smith TCAD, Synopsys, Inc. Date: Feb 21, 2006 Time: 4:15 pm - 5:05 pm Place: Hewlett 102 Abstract: The rapid rise of standby power in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Several technology boosters have been proposed to enable incremental performance improvements at similar off-state leakage. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective and relatively easy-to- integrate approach. In this talk we review the major impacts of strain on device fabrication and device characteristics, and we describe how these are addressed in TCAD simulations. We review how subsequent changes in carrier repopulation, effective mass, and scattering enhance, or degrade, the mobility and shift the threshold voltage for various stress configurations. In this context, optimizing the enhancement of the low-field mobility can be viewed as an exercise in band structure engineering. For high-field transport, we use Monte Carlo device simulation to investigate the impact of strain on velocity overshoot and drive current. Due to the large interaction range of stress in CMOS materials, ~2 um, the modeling of isolated devices is not sufficient to predict final circuit behavior. We also review some recent simulation studies we have performed to investigate the impact of circuit layout on channel stress and circuit performance. Biography: Lee Smith received a B.S. degree in physics from the University of Florida in 1989 and a Ph.D. degree in physics from Stanford University in 1997. In 1998 he joined the TCAD department at Synopsys, Inc. as an R&D engineer developing models and algorithms for numerical device simulation. Dr. Smith is currently a Staff R&D Engineer in the TCAD DFM Solutions Group at Synopsys engaged in model development for simulating advanced CMOS devices and addressing issues related to design-for-manufacturability. From mahnaz at stanford.edu Wed Feb 22 09:46:06 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Wed, 22 Feb 2006 09:46:06 -0800 Subject: YES OVen Message-ID: <43FCA35E.9090101@stanford.edu> Hello all, We found brunet resist in the YES oven this morning although Mario tried hard to get it off; you will see the residue of it in the system. Wafers with resist or any sort of polymer are not allowed in the YES oven, period. If you need to go in the oven you have the 90 C and 110 C oven and Mahnaz's Oven and not mentioning 6 other hot plates in the litho area. If you are confused ask me , I will answer it for you. Can some one tell me what is going on? Between Mary and I at least one email comes out daily about some mischief. HELP ME, I am not able to handle this any more. Mario and I trying very hard to keep as many equipments up as possible and I found this kind of behavior unfair. mahnaz From xinranw at stanford.edu Wed Feb 22 15:26:16 2006 From: xinranw at stanford.edu (Xinran Wang) Date: Wed, 22 Feb 2006 15:26:16 -0800 Subject: need help on the oxidation rate of Aluminum Message-ID: <22ffcd060602221526q68611b8av225d2c15ade5bdcf@mail.gmail.com> Dear Labmembers, I need the oxidation rate of aluminum at different temperatures in oxygen or in air. Does anybody know the oxidation rate or where to find it? Any input will be appreciated. Best wishes, Xinran -------------- next part -------------- An HTML attachment was scrubbed... URL: From kitu at stanford.edu Fri Feb 24 08:55:48 2006 From: kitu at stanford.edu (Aditi Chandra) Date: Fri, 24 Feb 2006 08:55:48 -0800 Subject: Reminder: University Ph.D. Oral Examination - Aditi Chandra Message-ID: <6.0.1.1.2.20060224084941.03a6c070@kitu.pobox.stanford.edu> Stanford University Ph.D. Oral Examination Aditi Chandra (Advisor: Prof. Bruce M. Clemens) Department of Materials Science and Engineering Stanford University Monday, February 27, 2006 9:30 AM (Refreshments served at 9:15 AM) McCullough Building, Room 335 "Synthesis, Characterization, and Applications of Au-Si Nanostructures" The pursuit of nanoscaled architectures has demanded new synthesis methodologies for creating and organizing metal particles. The challenge still remains to create well-defined structures with a tight control over particle size and distribution, especially for structures below 10nm. This talk will describe a new technique for creating Au-rich nanoparticles through the amorphous phase separation of Si-rich AuSi sputtered alloys. Using this technique, Au-rich nanoparticles, ranging from 2-3nm in diameter, can be routinely grown with particle densities on the order of 10^12 particles/cm^2. Both high resolution TEM and electron diffraction studies indicate that the Au-rich nanoparticles have an amorphous-like character. The phase separation process is modeled by a spinodal decomposition mechanism. Fastest growing composition wavelengths are calculated and are found to be in close agreement with the observed average particle-to-particle spacing, indicating that Au-rich particles can form by this second-order phase transformation. Extended anneals close to the eutectic temperature demonstrate the remarkable stability of these particles and suggest that these amorphous-like particles are thermodynamically stable due to their relatively low interfacial energy and high degree of curvature. Fundamental studies of annealed AuSi/Si multilayers reveal that Au-rich particles act as catalysts for the transformation of amorphous Si via metal-induced-crystallization. Crystalline silicon grains are modeled as tapered nanowires behind Au-rich nanoparticles and the free energy change is examined as a function of particle radius. It is calculated that particles with a radius less than 1.2 nm are unable to induce crystallization, and these findings are experimentally confirmed by TEM characterization. Finally, Au-rich nanoparticles are successfully incorporated into metal oxide semiconductor (MOS) structures for use as a charge trapping layer in floating gate devices. From high frequency capacitance measurements, MOS structures containing these particles show a significant hysteresis as compared to structures without nanoparticles. This difference in behavior is attributed to additional charge storage in either nanoparticle or nanoparticle interface states. For devices operating in the Fowler-Nordheim tunneling regime, a memory window of 0.6V can be achieved under a 10V programming voltage. This memory window can be enhanced with further increases of programming voltages and/or write times. This work represents one of the first examples of metal nanoparticles, formed by phase separation, utilized as a floating gate layer for non-volatile memory applications. -------------- next part -------------- A non-text attachment was scrubbed... Name: AChandra_defense_abstract.pdf Type: application/pdf Size: 34576 bytes Desc: not available URL: From pruitt at stanford.edu Fri Feb 24 11:28:26 2006 From: pruitt at stanford.edu (Beth Pruitt) Date: Fri, 24 Feb 2006 11:28:26 -0800 Subject: Prof Juergen Brugger, EPFL - SPECIAL SEMINAR-3/1/06... Message-ID: MEMS seminar next Wed... > >Good Morning! >We begin March with a special Guest Lecturer, >Professor Juergen Brugger, from the Swiss >Federal Institute of Technology (EPFL), >Lausanne, Switzerland. > > > Please save the date: >Your presence will help in making the seminar a >success. Please see abstract below: > > >SPECIAL SEMINAR > >Wednesday, March 1, at 4:15 pm >Building 300, Room 300 >Refreshments served beforehand at 4:00 pm > > >Professor Juergen Brugger, Ph.D. > >Microsystems Laboratory >Swiss Federal Institute of Technology (EPFL) >Lausanne, Switzerland > > >Microtools for nanotechnology: bridging gaps > > >ABSTRACT > >MEMS tools are ideal to bridge the gap from >macro to nanoscale, and vice-versa. This talk >will start with an overview of our recent >research and engineering activities at EPFL in >the field of MEMS-based devices for >nanotechnology. We have further developed >scanning probe based systems by adding new >materials (polymers (SU-8) and metals (W, Pt)) >to the toolbox of tips and cantilevers allowing >to further expand the range of mechanical >properties, tip radius, and probe-surface >interaction. One particular example is a new >generic fabrication process for cantilevers >combining SU-8 (a photostructurable polymer) >with integrated/embedded electrodes useful for >sensing function [1], e.g. micro-four point >probes with reduced probe-to-probe spacing and >reduce compliance for soft surfaces [2], a probe >made of W thin film [3] and miniature >Hall-sensors for non-invasive magnetic field >sensing [4]. Other types of MEMS-for-NANO >devices are ultra-thin mechanical membranes that >we use to shadow deposit material by a so-called >nanostencil lithography [5]. Here, a patterned >silicon nitride thin membrane is used as >shadow-mask to structure surfaces at the >micron-scale down to sub-100 nm. The method does >not require resist-based steps (spinning, >baking, solvents, etc.), hence it can be applied >to all sort of substrates, including mechanical >fragile and bio-chemically functionalized >surfaces. Nanostencil lithography is promising >for rapid prototyping as it allows for flexible >creation of customized nanostructures in >laboratories that do not have access to high-end >lithography tools. It enables combinatorial >material science, as well as a low-cost >replication methods to scale up nanopatterning. >I will also show an example that it can be used >for the fabrication of cantilever and bridges in >the sub-micron scale for NEMS and as post-CMOS >nanopatterning method featuring 1 micron >alignment accuracy on 100 mm wafer scale.... but >I will also discuss the current limits and >challenges ahead to make it a reliable method. > >[1] Schahrazede Mouaziz et al. "Polymer-based >cantilevers with integrated electrodes", JMEMS >(in press) >[2] S. Keller, et al., "Microscopic four-point >probe based on SU-8 cantilevers", Review of >Scientific Instruments, 76(12), 125102 (2005) >[3] J.A.J. Steen et al. "Electrically conducting >probes with full tungsten cantilever and tip for >scanning probe applications", Nanotechnology (in >press) >[4] G. Boero et al. "Submicrometer Hall devices >fabricated by focused electron-beam-induced >deposition", Applied Physics Letters, 86(4), >042503, (2005) >[5] M.A.F. van den Boogaat et al. >"Deep-ultraviolet-microelectromechanical systems >stencils for high-throughput resistless >patterning of mesoscopic structures", Journal of >Vacuum Science and Technology B, 22(6), pp. >3174-3177 (2004) > > >Biography > > J?ergen Brugger received a Ph.D. degree in 1995 from the University of Neuchatel, Switzerland for a work on microfabricated tools for the atomic force microscope, which included a one-year period at the Hitachi Central Research Laboratories, Tokyo, Japan. He then joined the IBM Zurich Research Laboratory in R?schlikon, Switzerland, working on the parallel AFM-based data storage project "Millipede". >From 1998 to 2001 he was directing the "NanoLink" Strategic Research Orientations at the MESA+ Research Institute, University of Twente, The Netherlands. In September 2001 he was appointed Assistant Professor "tenure track" at the EPFL. His main professional interests include the development of new tools for nanoscience and engineering techniques at the mesoscopic length-scale, in particular to develop methods for accessing the nanometer scale (top-down), and to combine them with self-assembly strategies (bottom-up), and to bridge life-science with solid-state devices at the micrometer and sub-micrometer scale. He has published over 50 journal papers, is (co-)inventor of 8 patents, and received two IBM research awards. His private pursuits include outdoor sports such as biking and mountaineering as well as indoors sports such as the combination of Single Malts and Jazz music. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 5f6004.jpg Type: image/jpeg Size: 23180 bytes Desc: not available URL: From mtang at stanford.edu Fri Feb 24 15:32:02 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 24 Feb 2006 15:32:02 -0800 Subject: Fire Extinguisher Training Available Message-ID: <43FF9772.2000508@stanford.edu> Greetings labmembers -- In our continuing efforts to improve safety, we'd like to invite interested labmembers to join us in a class on how to use a fire extinguisher. Everyone who's done this says it's loads of fun -- not to mention that it's an awfully handy skill to have when you need it. But seriously, we often forget that SNF is chock-full of hazards, and despite all the engineering controls and safety training in the world, accidents may still happen... For a sobering example of what can result from (what was thought to start out as) a small fire in a microfab lab, take a look at this: http://www.flickr.com/photos/johnbullas/58459134/in/set-1264633/ The class is scheduled to take place on Wednesday, March 8, at 10 am. The session will take one hour. (The class may be postponed if the weather conditions dictate.) We have a few spaces left in this session. If you are interested, please let me know. And if there's enough interest, we'll schedule another class in a couple of weeks. Thanks for your attention! Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Sat Feb 25 09:54:49 2006 From: mtang at stanford.edu (Mary Tang) Date: Sat, 25 Feb 2006 09:54:49 -0800 Subject: Fire Extinguisher Training Message-ID: <1140890089.440099e9a3c6b@webmail.stanford.edu> Greetings labmembers! Gee, I'm surprised at everyone's enthusiasm for fire extinguisher training - (and I'm sure it's because we all take our community responsibilities very seriously -- not at all because we'd enjoy a good fire.) The response has been great -- we not only filled up the remaining spots in this next session, but have enough to schedule another one. If you emailed me and received an email confirming your registration for the class on March 8, then you are registered (you'll receive a reminder a day or two in advance -- and if you can't make it, please let me know.) If you emailed me, but haven't received a confirmation email, I've just put your name on the list for the next session. I'll send another email out to you later this week, once a date/time is confirmed with the instructor (right now, we're aiming for some time during the week of March 20) and you can let me know if you would still like to attend. If you haven't emailed, but are interested in this next session, then please just send me an email and I'll get back to you once the next class time is confirmed. Thanks for your support for lab safety! Mary From alirezaa at stanford.edu Sun Feb 26 19:11:24 2006 From: alirezaa at stanford.edu (Alireza Khalili) Date: Sun, 26 Feb 2006 19:11:24 -0800 Subject: missing LOR bottle Message-ID: <6.2.5.6.2.20060226185857.03554ba8@stanford.edu> Hi everybody, We had an LOR-10B bottle (lift-off layer) that used to sit in the resist cabinet but is missing now. I was wondering if anybody knows where it may be... Much Thanks, --Ali From open4891 at stanford.edu Mon Feb 27 18:25:11 2006 From: open4891 at stanford.edu (Hideo Iwase) Date: Mon, 27 Feb 2006 18:25:11 -0800 Subject: Dry etching of Al or Ag film Message-ID: <1141093511.4403b487547e0@webmail.stanford.edu> Dear labmembers; I would like to etch silver or aluminum film in PlasmaQuest. Does anyone have experience of that? I would be grateful if someone would let me know the etching conditions for these films. Details of my experiment are as follows; material of film: Al or Ag thickness of film : 20-100 nm. Mask : PMMA (t=300 nm) substrate: GaAs wafer Patterns: Ph.C-like (a =250 nm, ? = 50-150 nm) Any suggestion is greatly appreciated. Best Regards; Hideo Iwase. Vuckovic group in Ginzton Lab. From fely at gloworm.Stanford.EDU Mon Feb 27 09:25:36 2006 From: fely at gloworm.Stanford.EDU (Fely Barrera) Date: Mon, 27 Feb 2006 09:25:36 -0800 Subject: EE 310 Seminar, February 28, 2006 Message-ID: <200602271725.k1RHPaOV004139@gloworm.Stanford.EDU> Title: IC Foundry Challenges & Strategy Date: Feb 28, 2006 (Tuesday) Time: 4:15 pm - 5:05pm Place: Hewlett 102 Abstact: This talk will first describe the past evolution and future outlook of IC foundry industry. I will then discuss the challenges of IC foundry from market, capacity, and IDM competition as well as TSMC's strategy to face the challenges. Biography: Konrad Young received the Ph.D. degree in Electrical Engineering from the University of California, Berkeley, in 1986. From 1986 to 1989, he was with Lincoln Laboratory, working on silicon-on-insulator device technology and 193nm lithography project. He joined Hewlett Packard Palo Alto research group in 1989 as a member of technical staff, involving in 0.5um and 0.35um logic technology development. In 1994, he was with Chartered Semiconductor Manufacturing, Ltd. (CSM), as Fab engineering manager on yield enhancement and product engineering. Since 1995, he has been with Winbond Electronics Corp. as memory technology development director, and then transferred to Worldwide Semiconductor Manufacturing Corp.(WSMC) as Fab engineering director. He joined Taiwan Semiconductor Manufacturing Co.(TSMC) in 1998, in charge of 0.18um, 0.13um, and 65nm platform technology development and R&D infrastructure program. He moved to TSMC San Jose office in Nov. 2005 and now is the director of Mixed-Signal/RF Program and University Relationship.