EE 310 Seminar, TODAY at 4:15 pm

Fely Barrera fely at gloworm.Stanford.EDU
Tue Feb 21 09:04:11 PST 2006


Title: TCAD Modeling of tress-Engineered MOSFETs

Speaker:Lee Smith
TCAD, Synopsys, Inc.

Date: Feb 21, 2006
Time: 4:15 pm - 5:05 pm
Place: Hewlett 102

Abstract:

The rapid rise of standby power in nanoscale MOSFETs is slowing
classical scaling and threatening to derail continued improvements in
MOSFET performance. Several technology boosters have been proposed to
enable incremental performance improvements at similar off-state
leakage. Strain-enhancement of carrier transport in the MOSFET channel
has emerged as a particularly effective and relatively easy-to-
integrate approach. In this talk we review the major impacts of strain
on device fabrication and device characteristics, and we describe how
these are addressed in TCAD simulations. We review how subsequent
changes in carrier repopulation, effective mass, and scattering
enhance, or degrade, the mobility and shift the threshold voltage for
various stress configurations. In this context, optimizing the
enhancement of the low-field mobility can be viewed as an exercise in
band structure engineering. For high-field transport, we use Monte
Carlo device simulation to investigate the impact of strain on
velocity overshoot and drive current. Due to the large interaction
range of stress in CMOS materials, ~2 um, the modeling of isolated
devices is not sufficient to predict final circuit behavior. We also
review some recent simulation studies we have performed to investigate
the impact of circuit layout on channel stress and circuit
performance.

Biography:

Lee Smith received a B.S. degree in physics from the University of
Florida in 1989 and a Ph.D. degree in physics from Stanford University
in 1997. In 1998 he joined the TCAD department at Synopsys, Inc. as an
R&D engineer developing models and algorithms for numerical device
simulation. Dr. Smith is currently a Staff R&D Engineer in the TCAD
DFM Solutions Group at Synopsys engaged in model development for
simulating advanced CMOS devices and addressing issues related to
design-for-manufacturability.





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